eda各种触发器设计

上升沿触发的D触发器有一个数据输入端D，时钟输入端CLK，数据输出端Q，表1是它的真值表。

use ieee.std_logic_1164.All;

entity dailin is

port(clk,d:in std_logic;

q:out std_logic);

end;

architecture bhv of dailin is

signal qq:std_logic;

begin

process(clk)

begin

if clk'event and clk='1'

then qq<=d;

end if;

end process;

q<=qq;

end;

JK触发器的种类很多，可以从不同的真值表，写出不同的JK触发器的设计程序。在此设计一个通用的JK触发器，表2是它的真值表。

use ieee.std_logic_1164.all;

entity dai is

port(j,k,clk:in std_logic;

q,qn:out std_logic);

end dai;

architecture behav of dai is

signal q_temp:in std_logic;

signal jk:std_logic_vector(1 downto 0);

begin

jk<=j&k;

process(jk,clk)

begin

if clk'event and clk='0'then

case jk is

when "00"=>q_temp<=q_temp;

when "01"=>q_temp<='0';

when "10"=>q_temp<='1';

when "11"=>q_temp<=not q_temp;

when others=>q_temp<=null;

end case;

q<=q_temp;

qn<=not q_temp;

end if;

end process;

end behav;

在D触发器和JK触发器的基础上设计其他类型的触发器，如T触发器，带异步复位、置位的D触发器。

T触发器的条件为：T=1时，q<=not q，在时钟上升沿赋值。

T=0时，q<=q，在时钟上升沿赋值。

library ieee;

use ieee.std_logic_1164.all;

entity dai is

port(t,clk:in std_logic;

q,qn:out std_logic);

end dai;

architecture behav of dai is

signal q_temp:std_logic;

--signal jk:std_logic_vector(1 downto 0); begin

process(t,clk)

begin

if clk'event and clk='1'then

case t is

when '0'=>q_temp<=q_temp;

when '1'=>q_temp<= not q_temp;

when others=>q_temp<=null;

end case;

q<=q_temp;

qn<=not q_temp;

end if;

end process;

end behav;

library ieee;

use ieee.std_logic_1164.All; entity dai is

port(clc,pset,clk,d:in std_logic;

q:out std_logic); end;

architecture bhv of dai is signal qq:std_logic;

begin

process(clc,pset,clk)

begin

if clc='0' then qq<='0';

elsif pset='0'then qq<='1'; elsif clk'event and clk='1'

then qq<=d;

end if;

--end if;

--end if;

end process;

q<=qq;

end bhv;