sigma delta adc

Design and Imple Bit Second-Ord S

J

VTU exte Abstract — In this paper, a technique continuous-time band-pass Sigma-Delta conver presented. The conversion from discret loop-filter transfer function into continuous-done by using Impulse-invariant-tran transconductor-capacitor filter is used to imp time loop-filter. A latched-type comparator and flop are being used as the quantizer of converter. The decimation filter is designed by a FIR filter for high-speed. A full adder cell and are used as basic building blocks of CIC Filter a 8 bit second-order continuous Sigma-Delta co been implemented in Cadence using 180nm CM the total power consumption is 34.48 mW. At a V, the maximum SNR is measured to be 4measured to be 8.29 bites, propagation delay 2.56ns which corresponds to a resolution of 8 bit

Index Terms — Analog-to-digital converter,Sigma-Delta ADC, Decimation Filter, Sigma-D I. INTRODUCTION

Architecture for Radio communication r

proposed in literature [1] and its block dia Figure 1. As shown in figure 1 the antenna and process the signal and fed to sigma-del

analog signal to digital signal. The m converter to be used for this narrow-band at 70MHz is a 8-bit band-pass Sigma-De

data converter is more desirable becaus higher resolution while consuming less pow

Fig. 1: Block diagram of the Single hig

architecture. [1]

The Band-pass Sigma-Delta ADC are usuall

switched-capacitor (SC) [2] technique ementation of Telescop der Continuous-Time B Sigma-Delta ADC

Jamuna G, Siva Yellampalli, Swetha S, nsion centre, UTL Technologies Ltd, Bangalore.

e to design the 8 bit rters for 70 MHz is te-time (z-domain) -time (s-domain) is nsformation. The

plement continuous-d a TSPC D Flip-of the Sigma-Delta a CIC Filter and an a TSPC D Flip-flop and FIR Filter. The onverter circuit has MOS technology and a supply voltage of 3 9.92 dB, ENOB is

is measured to be

ts. r, Continuous Delta modulator. receiver has been agram is shown in receiver the signal lta ADC to convert most optimal data signal application

elta ADC[1]. This se it can achieve

wer[1].

gh-IF receiver ly implemented by . However, SC implementations is limited in the modulators cannot be too hi the double-sampling technique the center frequency of the ban below 50 MHz. As mentioned switched-capacitor band-pass operate above 50MHz. To achi a continuous-time filter is nee the design and measuremen

Continuous-time band-pass Sig

shown in figure 1. As the design targets[1], the co eight bits of resolution, which is and distortion ratio (SNDR) of kHz bandwidth. For a 3V sup consumption is desired to be les The transformation from discre the design of the band-pass Sigm in section II. The circuit design Sigma-Delta modulator is descr designs for Decimation Filter ar

experimental results of the sigm

Section V. Finally, we summari

II. TRANSFORMATION F SIGMA-DELTA ADC TO SIGMA-DE The block diagram of the band-shown in Figure 2[1]. H(z) or H loop-filter depending on whethe time or continuous-time, res discrete-time band-pass Sigma-with a transfer function H(z) =z

Fig. 2: Block diagram of a band pic OTA in 8 Band-Pass

that the sampling frequency of

igh (below 50MHz). Even using e [3] or 2-path technique [4], nd-pass signal is still limited to

d abov

e discrete-time system or

Sigma-Delta modulator cannot ieve frequencies above 50 MHz ded. In this paper we presents

nt of a 8 bit Second-order gma-Delta ADC for the receiver onverter needs to have at least s equivalent to a signal-to-noise f better than 49 dB for a 200

pply voltage, the total power ss than 75 mW . ete-time to continuous-time for ma-Delta ADC [7] is described ns for the implementation of the ribed in section III. The circuit re described in section IV. The ma–delta ADC are presented in ze and conclude our work. FROM DISCRETE-TIME O CONTINUOUS-TIME ELTA ADC -pass Sigma-Delta modulator is H(s) are the transfer function of er the modulator is discrete-spectively. The second-order -Delta modulator implemented

-2/ (1+z -2)[1].

d-pass Sigma-Delta ADC [1]

The continuous-time filter H(S) responds t

continuously, unlike the switched-capaci discrete in nature. Therefore, a continuous-t has to be designed according to the DAC ou design a continuous-time modulator, the DA should be defined and its waveform should b

A good performance 1-bit DAC can be i

a zero-order-hold circuitry with a tran ZOH(s)=1-e -sT /s [1] where T is the Afterwards, a disc rete-time Z-domain to c

domain transformation should be done in or continuous-time band-pass Σ? modulato transformations can be considered: bilinear impulse-invariant-transformation. Bilinear transformation maps all frequencies

the Z-domain and vice versa, but the fre linearly mapped[1]. Impulse-invariant-transf frequencies linearly from –πfs/2 to frequencies will be aliased into the t therefore, anti-aliasing the signal is importa transformation[1]. There is a 70 MHz band-p the modulator that served the anti-aliasing Single high-IF receiver. Therefore, for desig impulse-invariant-transformation was chosen

?

1)

where H(z) is the discrete-time transfer loop-filter in the modulator, H(s) is th transfer function for the loop-filter, and 1-e -function of the DAC in the loop where T=1/In practical implementation, the quantizer With an extra one delay, the discrete-time a transfer function become[1].

III. CIRCUIT DESIGN FOR THE IMPLEM

SIGMA-DELTA MODULATOR.

In this section each block of the band pass as shown in figure 2[1] are described in deta

A. G m-C loop filter

A transconductor-capacitor (Gm-C) filter is the continuous-time loop-filter. Figure 3 diagram of the loop-filter, and Eq.

corresponding transfer function implemented

to an input signal itor filter that is time Σ? loop-filter tput waveform. To C transfer function

be considered. implemented using nsfer function of

sampling period.

continuous-time S-rder to implement a or. Two common transformation and s in the S-domain to equencies are non-formation maps the πfs/2 while other transformed band; ant when using this pass IF filter before g filter purpose for gn simplicity[1], the for modulator:[1] ) r function of the

he continuous-time

-sT

/s is the transfer fs .

is not delay-free. nd continuous-time

MENTATION OF sigma delta ADC

ail. used to implement shows the block (3) shows the

d.

Fig. 3: Block diagram of the loo

The basic block diagram of th capacitor.The Gm-cell is des Figure 4 shows the schematic circuit implementation in Caden

Fig.4: Schematic of the CMOS

B. Quantizer Design

Fig.5: Block diagram of quanti

The block diagram o figure 5. From figure 5 w components comparator and sample-and-hold function and quantizer, the latched-type co

Figure 6 depicts the Schemati Comparator in the quantizer des op-filter[1].

. .

.

.

3 he loop-filter are Gm-cell and signed using telescopic OTA. of the CMOS telescopic OTA nce.

Telescopic OTA[15].

izer. of the quantizer is shown in

we can see that it has two D-flip flop. To combine the the comparator function in a

omparator is the best choice. ic of the CMOS latched-type sign.

Fig. 6: Schematic of the CMOS latched-type Comparator[1].

In order to convert the return-to-zero (RZ) output of the

comparator to a NRZ output, a D flip-flop is added after the

latched-type comparator a TSPC D flip-flop is chosen. Figure 7

shows the schematic of the design of the TSPC D flip-flop.

Fig. 7: Schematic of the TSPC D flip-flop[1].

This D Flip-flop design also used in designing of Decimation Filter there we using Vout as output but in Quantizer Design in order to convert the return-to-zero (RZ) output of the comparator to the NRZ output we considering Vout’ as output. A continuous DAC is required for implementation of the Σ? modulator. The DAC should be linear and fast, therefore, 1-bit quantizer architecture is chosen and hence a 1-bit DAC are designed. The feedback DAC for the Σ? modulator using 180nm is implemented by a simple differential-pair to convert the output voltage to a current level. The adder is done by current addition of the Gm-cell current output and the current output of the DAC. Figure 7 shows the circuit of the Gm-C loop-filter with the feedback DAC. Figure 9 shows the schematic of CMOS current steering feedback DAC

Fig. 8: The circuit of the Gm-C loop-filter with the feedback

DA C

IV. CIRCUIT DESIGN FOR DECIMATION FILTER

The Decimation filter for the delta-sigma modulator output is implemented as a Complex low pass filter (LPF), i.e., the input stream of band pass signal is modulated into two low pass streams and filtered separately. This low pass filter has as its first stage a CIC filter followed by FIR filters for compensation and band limitation to eliminate aliasing caused by down sampling. The realization of the filter using full adder and the D flip-flop is presented in the following sections.

A. F ull Adder Pass transistor logic has high logic functionality. Hence Full adder designed with a 16 transistors in pass-transistor style. Figure 10[14] shows the 16-Transistor Full Adder Cell implementation in Cadence tool. The TSPC D flip-flop is used for Digital Decimation

filter design.

Fig. 10: The Schematic of 16-Transistor Full Adder Cell implementation in Cadence tool[14].

B. CIC Filter The CIC filter receives the samples from the modulator and operates at the highest sampling frequency of the filter. This filter needs to attenuate the quantization noise that aliases into the desired band of the modulator and hence needs to be of a greater order than the modulator. The sigma-delta modulator

whose output serves as the input to the filter is of third order.

For a decimation factor of 2, the transfer function[14].

H(z) = (1 + Z -1)k (4) where k is the order of the filter.

The presence of integrators in the filter transfer function leads to the filter output word length being greater than that of the input. This bit growth is given as,

B 0 = k.log 2 (N) +B i (5)

Where k is the filter order, N is the decimation ratio, Bi is theinput word length and Bo is the output word length.

Figure 11 illustrates the schematic of the basic computational element of CIC Filter. And the realization of the third order filter using a cascade of the computational element is shown in Figure 12.

Fig. 11: Basic computational element of CIC filters.

Fig. 12: Schematic of third Order CIC Filter

C. FIR Filter The FIR filter following the CIC filter is used to remove the ripples caused by the CIC filter in the frequency response in the desired band. The CIC filter does not have a flat pass band response. The magnitude response droops slightly toward the edge of the pass band. The transition from the pass band to the stop band for the CIC filter is not smooth and sharp. The FIR

filter with a linear response is used to compensate for these

shortcomings of the CIC filter. It is also used to limit the

bandwidth so that the high frequency components do not alias into the pass band.

The 1-bit FIR implementation is shown in Figure 13. It is realization with the full adder cells acting as 3-2 compressors. The flip-flops serve as delay elements as their output appears one clock cycle after the input is latched. The delayed outputs are added with the current value of the input and the resulting output is fed to the next delay stage. The final output has a two bit output for each bit of input. These are added together using a ripple carry adder (RCA) and the final output generated. The schematic of the ripple carry adder is shown in Figure 14. From this FIR Filter we can achieve the decimation ratio 2. The output word length is limited to 4 bits. The schematic of the 4-bit filter is shown in Figure 15.

Fig. 13: Schematic of the 1-bit FIR filter

Fig.14: Schematic of the Ripple Carry Adder

(RCA)

Fig. 15: Schematic of the 4-bit fir filter

V. EXPERIMENTAL RESULTS

The Figure 16 shows the test circuit of 8 bit Sigma-delta ADC Circuit design. The transient simulation results of the circuit are shown in Figures 17 for a time interval 100 ns.

Fig. 16: Test circuit of 8 bit Sigma-delta ADC Circuit Fig. 17: Transient response of 8 bit Sigma-delta ADC Circuit

Fig. 18:Power simulation result of 8 bit Sigma-delta ADC

The above Figure 18 shows power simulation result of 8 bit Sigma-Delta ADC. The corresponding power value of the result waveform is 34.48e-3 (34.48 mW).

Table 1: Summarized simulation results of the 8 bit Sigma-

delta ADC

The Table 1 shows the summarized simulation results of the 8 bit Sigma-delta ADC

VI. CONCLUSION

The design and experimental results of a 8-bit continuous-time band-pass Sigma-Delta ADC has been presented. This ADC is suitable for Single high-IF receivers. It has been shown that the continuous-time Sigma-Delta ADC contains an implicit anti-alias filtering in comparison to the discrete-time (switched-C) ADC, which is a significant advantage for band-pass ADC’s.

The proposed Sigma-Delta ADC can achieve a maximum SNDR of 49.92 dB, while operating at 3 V and consuming only 34.48 mW, which is at least 3 times smaller than

the others.

ACKNOWLEDGMENT

I feel glad to take this opportunity to thank the professor and Principal, Dr. V. Venkateshwarlu, VTU Extension Centre, UTL Technologies Ltd., Bangalore for taking keen interest and providing encouragement in my project work. Also, I would like to thank the teaching and non-teaching staff of VTU Extension Centre, UTL Technologies Ltd, Bangalore

for encouraging this research work.

REFERENCES

[1] Issac Hsu, and Howard C. Luong. “A 70-MHz Continuous time

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[3] S. Bazarjani & M. Snelgrove, “A 40 MHz IF Fourth-order

Double-Sampled SC Bandpass Sigma-Delta Modulator”, Proceedings

of IEEE International Symp. on Circuits & Systems, June 1997.

[4] A.K.Ong & B. A. Wooley, “A two-path bandpass Sigma Delta

modulator for digital IF extraction at 20 MHz”, IEEE J. of Solid-State

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[6] Kim D.D., Brooke M.A., “A 1.4G samples/sec comb filter design for

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[7] Steven R. Norsworthy., Richard Schreier., & Gabor C. Temes.

Delta-sigma data converter theory, Design , and Simulation , New

York: IEEE press,1996

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Technology CMOS

180nm CMOS

180nm

CMOS

180nm

CMOS

180nm

CMOS

180nm

CMOS

0.5μm

CMOS

0.5μm

CMOS

180nm

CMOS

180nm

Operating

frequency

560MHz 560MHz 5 MHz 3.2 MHz 24khz 400MHz 280MHz 360MHz 800MHz

Input

frequency

560 MHz 560 MHz 5MHz - - 100MHz 70MHz - -

Output frequency 140

MHz

140MHz

- - - - - - -

Decimation

factor

4 4 1 1 - 4 2 - -

ENOB 8.56 bites 8.29 bites - - - - - 10.1bites 11.07

bites

SNR 35.13 db 49.92db - 98 db 92.5 db 45 db 42 db 62.5 db 68.4 db Power 57.9 mW 34.48

mW

2.086mW 60μW 110μW 330mW 39mW 183mW 160mW

Power supply 3v 3v 1.8v 1.8v 1.8v 2.7/3.3v

2.5v 1.8v 1.8v

Propagation delay 3.09ns

2.56ns

- - - - `- - -

[8] S. Bazarjani & M> Snelgrove, “A 40MHz IF Fourth-order double

sampled SC Bandpass ∑? Modulator”. Proceedings of IEEE

International Symp. On Circuits & Systems, June 1997.

[9] Y. S. Shu, J.Kamiishi, K. Tomioka, K. Hamashita, and B. S. Song,

“LMS based noise leakage calibration of cascaded continuous time ΣΔ

modulators,” IEEE J. Solid-State Circuits, vol. 45, no. 2, pp. 368-379,

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[10] C. Y. Lu, J. F. Silva-Rivas, P. Kode, J. Silva-Martinez, and S. Hoyos,

“A sixth-order 200 MHz IF bandpass sigma-delta modulator with over

68 dB SNDR in 10 MHz bandwidth,” IEEE J. Solid-State Circuits,

vol. 45, no. 6, pp. 1122-1136, June 2010.

[11] Jaydip.H.Chaudhari PG Student L. C. Institute of Technology, Bhandu,

Gireeja D.Amin Assistant Professor L. C. Institute of Technology,

Bhandu Design and Simulation of 1-bit Sigma Delta ADC in 0.18um

CMOS Technology, International Journal of Computer Applications &

Information Technology Vol. II, Issue I, January 2013.

[12] Hamid Reza Sabouhi, Mohammad Honarparvar and Vahid

Sabouhi,A 60-μW, 98-dB SNDR and 100-dB Dynamic Range

Continuous Time Delta Sigma Modulator for Biological Signal

Processing in 0.18-μm CMOS, Journal of Basic and Applied

Scientific Research, 2012

[13] Pavan, S.; Krishnapura, N.; Pandarinathan, R.; Sankar, P. A power

optimized continuous-time ΔΣ ADC for audio applications. IEEE J.

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[15] Kush gulati and Hae-seung lee “A high-swing CMOS telescopic

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