32位异步(RISC)微处理器的新设计及其在FPGA上的应用(IJIEEB-V10-N1-6)

32位异步(RISC)微处理器的新设计及其在FPGA上的应用(IJIEEB-V10-N1-6)
32位异步(RISC)微处理器的新设计及其在FPGA上的应用(IJIEEB-V10-N1-6)

I.J. Information Engineering and Electronic Business, 2018, 1, 39-47

Published Online January 2018 in MECS (https://www.360docs.net/doc/694496704.html,/)

DOI: 10.5815/ijieeb.2018.01.06

Novel Design of 32-bit Asynchronous (RISC) Microprocessor & its Implementation on FPGA

Archana Rani

Faculty of Engineering and Technology, Manav Rachna International University, Faridabad, India

Email address: Archana.bhatia.pec@https://www.360docs.net/doc/694496704.html,

Dr. Naresh Grover

Faculty of Engineering and Technology, Manav Rachna International University, Faridabad, India

Email address: dean.academics@https://www.360docs.net/doc/694496704.html,.in

Received: 20 July 2017; Accepted: 12 September 2017; Published: 08 January 2018

Abstract—As the efficiency and power consumption plays an important role in electronic system design, an asynchronous design is used to reduce such challenges faced in synchronous architectures. The asynchronous processors have a number of advantages, especially in SoC (System on chip) including reduced crosstalk between analog and digital circuits, ease of integrating multi-rate circuits, ease of component reuse and less power consumption as well. This paper deals with the novel design and implementation of such type of asynchronous microprocessor by using VHDL on Xilinx ISE tool wherein it has the capability of handling even I-Type, R-Type and Jump instructions with multiplier instruction packet. Moreover, it uses separate memory for instructions and data read-write that can be changed at any time.

Index Terms—Asynchronous design, Processor, VHDL, MIPS, Synthesis & Simulation, Instruction data path, EDA Tools

I.I NTRODUCTION

Now- a- days computers are evolving using RISC (Reduced Instruction Set Computer) Architecture replacing stack architecture with the intention to displace the hypothetical, emulated computer by a real one. Instruction Set Architecture (ISA) design is the concept of CISC (Complex Instruction Set Computer) that emphasize more on each instruction using a wide range of addressing modes and number of operands in various locations in its Instruction Set. This leads to execution time to vary as instructions are not of fixed length, hence demanding a very complex Control Unit, which occupies a large area on chip. While on the other side, the RISC Processor has less number of Instructions. The fixed instruction length with more general purpose registers to support load-store architecture and simplified addressing modes. This makes individual instruction to execute faster in order to achieve a net gain in performance and an overall simpler design with less silicon consumption. The choice of an RISC has become more obvious with the increase in size and complexity of modern processors and software. The hardware designer has a substantial amount of freedom for design by making use of FPGA being much more aware of availability of resources and of its limitations than the software developer.

Before commencing the design of an asynchronous processor we have to first focus on the architecture of Asynchronous processor as well as the various steps involved in such designs in terms of the program cycle. This paper presents processor architecture design, its implementation followed by processor instruction set, data path flow for fetching unit, Register type, I-type and load /store type instruction flow. Thereafter this paper illustrates control unit design of processor that shows the controlling of signals for different units in processor design. Further, a complete internal structure is shown followed by features of novel processor architecture. In the end, results have been shown using implementation windows. The complete design has been written using VHDL and then simulated and synthesized by XILINX ISE tool.

A. Processor Architecture

The asynchronous processor internal operation is segmented into five pipeline stages and in each of them the operations of the tasks will be performed in the normal cycle of an instruction, i.e. search of the instruction (identified with the IF block), decoding of The instruction (identified with the ID block), execution of the operation (identified with the EX block), memory access (identified with the MEM block) and storage of the operation result (identified with the WB block) [24].

The first stage is Instruction Fetch that comprises of Instruction Memory, Program Counter, and Instruction Register. In this stage, a program counter will extract the next instruction from a location in program memory. It updates the program counter value with the next instruction location sequentially or the location determined by a branch. The second stage is instruction decoding which comprises of register file and the extender (sign & Zero). This stage determines the values

on which the control lines should be set as per the instruction. The third stage is the instruction execution stage, where ALU and necessary parts will come into action. In this stage, the instruction is actually sent to the ALU and branch locations are also calculated. The fourth stage is Memory execution stage for accessing of data from system memory. Finally, in Write back stage the values/data written back to the register(s).

Fig.1. Processing Stages

B. Instruction Set Format

The Asynchronous Processor has fixed width instructions (32- bit). There are 3 instruction types: I-type (Immediate), R-type (Register), J-type (Jump). Fig. 2 shows the format of I-type and R-type instructions. [23]

Opcode

RS

RT

Address/immediate

6 5 5 16

Fig.2. (a) I-Type Instruction

Opcode

RS

RT

RD

Shift

Function

6 5 5 5 5 6

Fig.2(b). R-Type Instruction

MIPS ( Microprocessor without Interlocked Pipeline Stages) are load/store architecture, meaning that all operations are performed on values found in local registers. The main memory is only accessed through load (copy value from memory to local register) and store (copy value from local register to memory) instructions. The fields in the MIPS instructions are the followings:

? OPCODE – 6-bit operation code

? RS – 5- bit specifier for source register ? RT – 5- bit specifier for target register

? RD – 5- bit specifier for destination register

? Address/immediate – 16-bit signed immediate

used for logical and arithmetic operands, load/store address offsets ? Shift – 5-bit shift amount

? Function – 6-bit code used to specify functions

II. I NSTRUCTION I MPLEMENTATION

Every instruction propagates in a specified sequence such as fetch, decode, execution & write back. There are three types of instruction(s) in processor/controller based system. These are I-Type, R-Type and Jump type instruction. The different type of instruction data paths has been depicted in figures 3, 4, 5 and 6.Figure 3 shows the data path for the fetching process. It depicts the flow of the various path involved in fetching. The figure 4 and 5 shows the register/memory pattern follows during the Register/Immediate type instruction execution. And at last figure 6 depicts the overall combined path flow for all type of instruction execution data path. A. Fetch Data path Flow

Figure 3 shows the Fetching of an instruction from memory. The PC (Program Counter) always indicates the location of the instruction to execute. The location is basically an Internal ROM where all instruction (to be executed) are stored at different locations. Once the PC fetches an instruction from its current value, the PC address automatically advances by 4. The order of the PC can be changed by the occurrence of the instruction stored in the memory block.

Fig.3. Fetch Data path

B. Register Type Data path Flow

The register type instruction(s) is the instruction involved with the data to be communicated to and fro from the internal (general purpose registers)/external registers (RAM). After being fetched, the instruction is bifurcated into fields i.e. Opcode (Store/shift/Add etc.), source and destination register location/data with some controlling signals named register write or read registers. Then the data or value of the specified register location will propagate through ALU for different operations to be performed.

Fig.4. R-Type Data path Flow

C. Load/Store Datapath Flow

Figure 5 shows the data path flow for the immediate instructions to load and store at various location, these locations may be any general purpose or any memory locations that can be addressed randomly.

Fig.5. Load/Store Datapath Flow

D. Multiple Instruction Datapath Flow

Fig.6. processing paths for all instructions

Table 1. Action for all instructions

Table 1 shows all actions necessary for the execution of an instruction (of any type) during each stage(s). To differentiate the type of instruction we had design one control unit which takes care of overall operation execution cycle. E. Control Unit Design

The design of control unit has been divided into various states through which it is going to generate the control signals for other components in the design, based on the current state and on the instruction code. Following are the control signals:

MemRead: if 1, read from memory;

MemWrite: if 1, write to memory;

RegDst: if 1, the destination number for the Write register comes from the Rd field; if 0, it comes from Rt field;

RegWrite:if 1, the general-purpose register selected by the Write register number is written with the value of the Write data input;

AluSrcA:(ALU Source A) if 1, the operand is A register; if 0, the operand is PC;

MemtoReg: if 1, it comes from Memory data register (MDR) and if 0, the value fed to the register file Write data input comes from ALUOut;

IRWrite:if 1, write instruction is performed in IR; PCWrite: if 1, update the PC;

The control unit is basically the part of our 32-bit asynchronous processor. The complete designs of processor architecture have been distributed into small units. Proposed design has various sub modules which are basically named as ALU control unit, RAM / ROM blocks, PC unit, Shift, Add, Multiplier units

for various

arithmetic and logical instruction. In the end, interfacing module for all the sub units is designed. As each unit has their own significance, the major role played by the control unit is to command/control the overall operation. Hence more emphasis has been given to this unit.

F. Processor Architecture

This section deals with the complete internal structure of our 32-bit Asynchronous Processor. All the various stage(s) required for an instruction processing is been identified by the call out(s) box(es). Figure 7 shows the internal architecture of Asynchronous processor, In this processor, fetching the instruction pointed by the Program counter goes to the next unit called decoder which generates the different values of the memory location, as per the instruction fetched from the previous unit. During this control unit has been designed in order to synchronize the various other units such as ALU, data memory or general purpose registers to properly execute the desired instruction. There are other units named as ALU, data memory, and some multiplexers to complete the execution cycle. The entire major units have been discussed previously.

.

Fig.7. Internal Structure of the Processor

III. F EATURES OF N OVEL P ROCESSOR

The 32-bit asynchronous processor has the capability of handling all types of instructions i.e. I-Type, R-Type, Jump Instructions and also multiply instructions packet. The multiplied result is stored until is needed irrespective of other instructions follows.

The proposed processor is using separate memory for instructions and Data. The capacity of instruction memory i.e. ROM is of 8192*32 in which 8192 are representing the locations where instructions are to be stored with 32-bit data. The structures of instructions are as per ISA (instruction set Architecture). For all stages, there is only one clock cycle needed, while the data memory has the capacity of 64K. Both memories are functioning in falling pulse. The other pulses are used for developing the necessary functions just like pipelining in order to make our processor core faster and much flexible. All I-type instructions are part decoded in the first stage and all R-type instructions are part decoded in ALU control unit. This reduces the complexity in main control unit. The complete processor core is designed in Xilinx ISE 14.x tool.

The so far studied processor architectures do not contain all instruction in a single architecture especially (Jump & Multiply instructions). Also while designing the whole processor core much more attention is given to design the proposed processor in such a way to optimize the core for much better results in terms of Area, Power or Delay.

IV. D ESIGN I MPLEMENTATION

The complete processor has been implemented on the Xilinx ISE tool. All the coding have been done in VHDL and simulated or verified by the XILINX ISIM. The following windows come from Xilinx simulator for various instructions Stored in Instruction memory. Figure 8 shows the project settings i.e. the target family Virtex-6, with device name XC6Vlx240T.

Fig.8. Project setting window in Xilinx ISE

A. Instruction Memory Window

Figure 9 shows the various instructions written into internal memory. From which PC fetches the instruction to be executed. In figure 10 the table shows the complete structure of the mnemonics for asynchronous processor instruction. The order of instruction execution can be changed as per the designers or consumer requirement. Although once written in Instruction memory the order of

the execution of instruction will be as per the order of the mnemonics appears. The Instruction memory is also known as code memory /ROM where all the instructions are going to be stored permanently. The overall execution of any instruction is always been started by the code/instruction memory. In the below figure we have shown some instruction mnemonics although we can store /provide various instruction up to 32 KB i.e. 8192 memory location available and on each location one can store up to 32 bit of data. Also, we are having 32*32 register for temporary storage of the output or any general purpose work. This is shown in figure 10.

Fig.9. Instruction Memory inferred in Xilinx ISE Tool.

Shamt -Shift amount, Func - Function

Fig.10. Mnemonics of Instruction

B. Register Bank Window

Figure 11 shows the internal register bank arrangements of the designed processor. By default, all the values in registers are (in 32-bit Binary) "0000000000000000000000000000". We kept some values during the operation of addition and subtraction so that we never get zero as an output. There are thirty-two, 32-Bit registers to temporary hold the data. These registers can be used in any type of addressing modes i.e. Immediate, Register Direct or Indirect addressing modes. The values in the corresponding registers will automatically update once the instruction will be fetched and executed.

Fig.11. Register Bank inferred in Xilinx ISE tool

V. S IMULATION R ESULTS

The simulation is carried out on Xilinx ISIM tool and results are shown in this section. Figure 12 shows the result with initial conditions i.e. Rst='0'. So that the processor comes into its initial state with the initial values in all types of the registers.

Fig.12. Simulation with initial Condition i.e. Rst=’0’.

Figure 13 & 14 shows the simulation result for loading of a number from memory to a register. The instruction for this is 8F890064 (10001111100010010000000001100100b), where 100011b is the Opcode, 11100 is source location, 01001b is Destination register location and rest is the immediate address from where data to be read. The instruction works as:

Rt = mem [rs(data)+64h] where rt= 1001b or 9(h/d), Rs =11100b or 1ch or 28d in register bank and having zero value. So the resultant address from where data to be fetched would be 64h+0h= 64h. The content of this 64h will be loaded into the 9 register in register bank.

Hex code: 8F890064, LW $s1, 100($s2) Load word

Fig.13. Register bank updated Value

Fig.14. Load data from memory

Figure 15, shows the simulation for the instruction to store some number from register to memory location. “AF890060”, is the mnemonics for this instruction. This will perform the storing the number from the specified location i.e. 1001 (9) to the address hold by the rs and constant value. The yellow marker shows this happening in the simulation cycle.

mem [rs+60h]= rt where rt= 1001b or 9(h/d),

Rs =11100b or 1ch or 28d in register bank and having zero value. Since Rt holds the value 30303030H, now this value is going to be written in the memory location. Hex Code: AF890060 SW $s1, 96($s2) Store word Fig.15. Storing of an immediate number

Fig.16. Addition of values from register bank

Figure 16 shows the simulation output of the Addition operation of the values stored into internal register bank. The opcode for this instruction is 2538820. The register location(s) are marked by blue color in the simulation diagram.

Fig.17. Subtraction of values from register Bank

The above figure shows the complete summary of our implemented design, which carries the information(s) about the number of resources i.e. inferred gates/FFs/dedicated LUTs, has been used by the implemented designed. Through this information, we can also put some extra efforts in the direction of optimizing our design for the best possible result.

Fig.18. Device Utilization Summary

A. Overall processor Simulation Results

Figure(s) 19 and 20 are showing the overall processor results. While initializing the processor with rst =’1’. Our processor starts fetching the instruction from ROM/ Instruction memory which contains the Store, Load word and Addition and Subtraction operation. Due to large simulation signals we had divided our simulation windows in two halves. The first half i.e. figure 19 shows the signals like clk, rst, Aluop, Alusw, AlusrcA, IRwrite etc. These signals are basically coming from the control Unit to bind the overall instruction execution. For simplicity we had taken out Bus_r(31:0) for the final output. Although we can verify these data into the internal memory location(s) or Register Memory Window.

Fig.19. Overall Processor Simulation result (1)

Fig.20. Overall Processor Simulation result (2)

The instr(31:26) signal shows the process of opcode fetching from Instruction memory, it starts from 8F, i.e.opcode for the loading of data into the memory, the next is AF for storing the data from memory, then 02 for Addition and so on. On every clock pulse the new instruction will be fetched and update automatically the instr(31:26) signal. This signal in simulation waveform is highlighted by the color RED.

The immed_addr(15:0) signal shows the immediate value for the use of ALU operations. This signal is highlighted by Yellow color in simulation waveform. The intermediate Bus (31:0) is showing the data output from the ALU after completion of any instruction. This is highlighted by the color white. At last the output from A showing by ALU_OUT(31:0) highlighted by the color Purple.

VI.C ONCLUSION

The 32-bit fully functional asynchronous processor has been designed using VHDL. A fully asynchronous processor has been implemented that is comprised of five stages. The work can be potentially improved by reducing I and R-type instructions. The functional simulation shows that proposed processor executes all the various instructions efficiently. The proposed design being an open core is more advantageous as compared to the existing commercial microprocessor for better understanding of internals of the asynchronous microprocessor.

F UTURE S COPE

The design of this 32-bit asynchronous microprocessor implemented using FPGA can be further optimized to reduce its power and area by using any of the following optimization techniques Technology mapping & Logic Optimization.

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Authors ’ Profiles

Ms. Archana Rani Bhatia is a Ph.D. A scholar from Manav Rachna International University, Faridabad. Had completed Post Graduation in Electronics Product Design and Technology from Punjab Engineering College Chandigarh in 2008 and did Graduation in Electronics and Communication Engineering, with sound

working experience over 6.6 years in various electronic works, related to Teaching, Research & Industry side.

Prof. (Dr.) Naresh Grover did his B.Sc (Engg.) in 1984 and M.Tech in Electronics and Communication Engineering in 1998 from REC Kurukshetra (Now NIT Kurukshetra). He has a rich experience of 33 years in academics. He has authored two books on Microprocessors and is a co-author of a

book on Electronic Components and Materials. His core area of interest is Microprocessors and Digital System Design. Presently he is Dean-Academics at Manav Rachna International University, Faridabad.

How to cite this paper: Archana Rani, Naresh Grover," Novel Design of 32-bit Asynchronous (RISC) Microprocessor & its Implementation on FPGA", International Journal of Information Engineering and Electronic Business(IJIEEB), Vol.10, No.1, pp.

39-47, 2018. DOI: 10.5815/ijieeb.2018.01.06

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Let AJAX change this text

接下来,在页面的 head 部分添加一个 AJAX - 创建 XMLHttpRequest 对象?Previous Page ?Next Page XMLHttpRequest 是 AJAX 的基础。 XMLHttpRequest 对象 所有现代浏览器均支持 XMLHttpRequest 对象(IE5 和 IE6 使用ActiveXObject)。 XMLHttpRequest 用于在后台与服务器交换数据。这意味着可以在不重新加载整个网页的情况下,对网页的某部分进行更新。 创建 XMLHttpRequest 对象

所有现代浏览器(IE7+、Firefox、Chrome、Safari 以及 Opera)均内建XMLHttpRequest 对象。 创建 XMLHttpRequest 对象的语法: variable=new XMLHttpRequest(); 老版本的 Internet Explorer (IE5 和 IE6)使用 ActiveX 对象: variable=new ActiveXObject("Microsoft.XMLHTTP"); 为了应对所有的现代浏览器,包括 IE5 和 IE6,请检查浏览器是否支持XMLHttpRequest 对象。如果支持,则创建 XMLHttpRequest 对象。如果不支持,则创建 ActiveXObject : var xmlhttp; if (window.XMLHttpRequest) {// code for IE7+, Firefox, Chrome, Opera, Safari xmlhttp=new XMLHttpRequest(); } else {// code for IE6, IE5 xmlhttp=new ActiveXObject("Microsoft.XMLHTTP"); } 在下一章中,您将学习发送服务器请求的知识。 AJAX - 向服务器发送请求 ?Previous Page ?Next Page XMLHttpRequest 对象用于和服务器交换数据。 向服务器发送请求 如需将请求发送到服务器,我们使用 XMLHttpRequest 对象的 open() 和 send() 方法: xmlhttp.open("GET","test1.txt",true); xmlhttp.send();

同步复位和异步复位的区别

针对数字系统的设计,我们经常会遇到复位电路的设计,对初学者来说不知道同步复位与异步复位的区别与联系,今天我对这个问题简要的阐述下,希望对初学者有一定的参考意义,若有不正确的地方愿大家明示。 同步复位原理:同步复位只有在时钟沿到来时复位信号才起作用,则复位信号持续的时间应该超过一个时钟周期才能保证系统复位。 异步复位原理:异步复位只要有复位信号系统马上复位,因此异步复位抗干扰能力差,有些噪声也能使系统复位,因此有时候显得不够稳定,要想设计一个好的复位最好使用异步复位同步释放。 同步复位与异步复位的优劣:异步复位消耗的PFGA逻辑资源相对来说要少些,因此触发器自身带有清零端口不需要额外的门电路,这是其自身的优势,通常在要求不高的情况下直接使用异步复位就OK。 下面我用verilog来演示下同步复位与异步复位。 同步复位的verilog程序如下: module D_FF (

//Input ports SYSCLK, RST_B, A, //Output ports B ); //========================================= //Input and output declaration //========================================= input SYSCLK; input RST_B; input A; output B; //========================================= //Wire and reg declaration //=========================================

Javascript基础

表JS基本类型有什么?引用类型有什么? 基本类型:number,string,boolean,undefined,null 引用类型:基本类型以外的都是引用类型,如object/array/function/date等等 关于基本类型与引用类型的区别可以详细看看@Naraku_的这篇文章: [ JS 进阶] 基本类型引用类型简单赋值对象引用 概况起来有这么几个要点: 1.我们无法给基本类型的对象添加属性和方法; var m1 = 123; https://www.360docs.net/doc/694496704.html, = 'abc'; console.log(https://www.360docs.net/doc/694496704.html,); //输出:undefined 2.基本类型对象的比较是值比较,而引用类型对象的比较是引用比较; var m1 = 123, m2 = 123; console.log(m1 === m2); //输出:true var o1 = {}, o2 = {}; console.log(o1 === o2); //输出:false 3.基本类型对象是存储在栈内存中的,而引用类型对象其实是一个存储在栈内存中的一个堆内存地址。 4.基本类型对象赋值时(执行=号操作),是在栈内存中创建一个新的空间,然后将值复制一份到新的空间里。 5.引用类型对象赋值时(执行=号操作),也是在栈内存中复制一份一样的值,但这个值是一个堆内存地址,所以被赋值的那个对象跟前者其实是一个对象。 var o1 = {}; var o2 = o1; https://www.360docs.net/doc/694496704.html, = 'abc';console.log(https://www.360docs.net/doc/694496704.html,); // --> abc console.log(https://www.360docs.net/doc/694496704.html,); // --> abc o2.age = '123';console.log(o1.age); // --> 123console.log(o2.age); // --> 123 JS中的常见对置对象类

2019年秋季考试《计算机应用基础》在线考核试题 微型计算机的微处理器是指

计算机应用基础 1 单选题 1 微型计算机的微处理器是指() A A 控制器和运算器 B CPU和I/O接口 C CPU和RAM D 控制器和主存 2 将文件移至剪贴板的快捷键是() B A Ctrl+S B Ctrl+X C Ctrl+V D Ctrl+C 3 在PowerPoint幻灯片中直接插入*.swf格式Flash动画文件的方法是() D A 设置按钮的动作 B 设置文件超链接 C “插入”选项卡中的“对象”命令 D “插入”→“视频”→“文件中的视频” 4 要清空开始菜单文档命令中保留的最近使用的文档名需通过() D A 资源管理器 B 控制面板中的“程序” C 桌面快捷菜单中的“属性” D 任务栏快捷菜单中的“属性”

5 Excel 2010中被选定的单元格区域自动带有() D A 闪烁边框 B 蓝色边框 C 红色边框 D 黑色边框 6 能够将高级语言源程序加工为目标程序的系统软件是() D A 编辑程序 B 汇编程序 C 解释程序 D 编译程序 7 计算机一次能处理数据的最大位数称为该机器的() A A 字长 B 字节 C 计算精度 D 总线宽度 8 建立新Word文档应该选择的选项卡是() C A 插入 B 审阅 C 文件 D 视图 9 在PowerPoint中插入幻灯片编号的方法是() B A 选择“格式”选项卡中的“幻灯片编号”命令 B 选择“插入”选项卡中的“幻灯片编号”命令

C 选择“视图”选项卡中的“幻灯片编号”命令 D 选择“幻灯片放映”选项卡中的“幻灯片编号”命令 10 进入PowerPoint 2010幻灯片母版的方法是() C A 按住Shifi键的同时再单击“普通视图”按钮 B 按住Shifi键的同时再单击“幻灯片浏览视图”按钮 C 选择“视图”选项卡下“母版视图”组中的“幻灯片母版”命令 D 选择“开始”选项卡下“母版视图”组中的“幻灯片母版”命令 11 在Word文档中插入页眉和页角应切换到() D A Web版式视图方式 B 大纲视图方式 C 草稿视图方式 D 页面视图方式 12 系统总线是微机的主要部件之一,目前在个人计算机中基本都使用() A A PCI总线 B ISA总线 C IDE总线 D USB总线 13 构成计算机物理实体的部件被称为() D A 计算机系统 B 计算机主机 C 计算机程序 D 计算机硬件 14 幻灯片版式的组成元素是() A

同步传输与异步传输的区别

在网络通信过程中,通信双方要交换数据,需要高度的协同工作。为了正确的解释信号,接收方必须确切地知道信号应当何时接收和处理,因此定时是至关重要的。在计算机网络中,定时的因素称为位同步。同步是要接收方按照发送方发送的每个位的起止时刻和速率来接收数据,否则会产生误差。通常可以采用同步或异步的传输方式对位进行同步处理。 1. 异步传输(Asynchronous Transmission):异步传输将比特分成小组进行传送,小组可以是8位的1个字符或更长。发送方可以在任何时刻发送这些比特组,而接收方从不知道它们会在什么时候到达。一个常见的例子是计算机键盘与主机的通信。按下一个字母键、数字键或特殊字符键,就发送一个8比特位的ASCII代码。键盘可以在任何时刻发送代码,这取决于用户的输入速度,内部的硬件必须能够在任何时刻接收一个键入的字符。 异步传输存在一个潜在的问题,即接收方并不知道数据会在什么时候到达。在它检测到数据并做出响应之前,第一个比特已经过去了。这就像有人出乎意料地从后面走上来跟你说话,而你没来得及反应过来,漏掉了最前面的几个词。因此,每次异步传输的信息都以一个起始位开头,它通知接收方数据已经到达了,这就给了接收方响应、接收和缓存数据比特的时间;在传输结束时,一个停止位表示该次传输信息的终止。按照惯例,空闲(没有传送数据)的线路实际携带着一个代表二进制1的信号,异步传输的开始位使信号变成0,其他的比特位使信号随传输的数据信息而变化。最后,停止位使信号重新变回1,该信号一直保持到下一个开始位到达。例如在键盘上数字“1”,按照8比特位的扩展ASCII编码,将发送“00110001”,同时需要在8比特位的前面加一个起始位,后面一个停止位。 异步传输的实现比较容易,由于每个信息都加上了“同步”信息,因此计时的漂移不会产生大的积累,但却产生了较多的开销。在上面的例子,每8个比特要多传送两个比特,总的传输负载就增加25%。对于数据传输量很小的低速设备来说问题不大,但对于那些数据传输量很大的高速设备来说,25%的负载增值就相当严重了。因此,异步传输常用于低速设备。 2. 同步传输(Synchronous Transmission):同步传输的比特分组要大得多。它不是独立地发送每个字符,每个字符都有自己的开始位和停止位,而是把它们组合起来一起发送。我们将这些组合称为数据帧,或简称为帧。 数据帧的第一部分包含一组同步字符,它是一个独特的比特组合,类似于前面提到的起始位,用于通知接收方一个帧已经到达,但它同时还能确保接收方的采样速度和比特的到达速度保持一致,使收发双方进入同步。 帧的最后一部分是一个帧结束标记。与同步字符一样,它也是一个独特的比特串,类似于前面提到的停止位,用于表示在下一帧开始之前没有别的即将到达的数据了。

Ajax的实现步骤

AJAX基本实现步骤 AJAX是异步通信的一种技术,主要实现技术是javascript+xml+html+css+服务端。在这里主要讨论客户端的操作。以下是客户端的实现步骤: 1、创建XMLHttpRequest对象(需要考虑各浏览器兼容的问题) 2、使用XMLHttpRequest对象打开一个连接(指定连接方式和连接地址以及是否同步) 3、设置请求的头部(请求的类型和请求的编码格式) 4、设置回调函数 5、发送请求 6、更新页面显示 实现详解: (1)、创建XMLHttpRequest对象(需要考虑各浏览器兼容的问题)。 具体实现: var xmlHttp; function createXMLHttpRequest() { //建立XMLHttpRequest try { xmlHttp= new XMLHttpRequest(); } catch (e) { try { xmlHttp = new ActiveXObject("Msxml2.XMLHTTP");

} catch (ee) { try { xmlHttp = new ActiveXObject("Microsoft.XMLHTTP"); } catch (err) { xmlHttp = false; } } } if(!xmlHttp) alert("不能创建XMLHttpRequest对象"); } createXMLHttpRequest(); 基本上,上面的码就能够实现在大部分浏览器中创建XMLHttpRequest对象。这一步的作用就是为了创建XMLHttpRequest对象,所以基本上不需要进行更改。 (2)、使用XMLHttpRequest对象打开一个连接(指定连接方式和连接地址以及是否同步) 具体实现: xmlHttp.open("POST","URL ",true); 调用XMLHttpRequest对象的open方法。第一个参数是提交数据的方式,取值为post/get;第二个参数是提交的目标页面(也就是用于处理提交数据的页面);第三个参数指定是否请求是异步的-缺省值为true,为了发送一个同步请求,需要把这个参数设置为false。 (3)、设置请求的头部(请求的类型和请求的编码格式)

同步通信与异步通信区别

同步通信与异步通信区别 1.异步通信方式的特点:异步通信是按字符传输的。每传输一个字符就用起始位来进来收、发双方的同步。不会因收发双方的时钟频率的小的偏差导致错误。这种传输方式利用每一帧的起、止信号来建立发送与接收之间的同步。特点是:每帧内部各位均采用固定的时间间隔,而帧与帧之间的间隔时随即的。接收机完全靠每一帧的起始位和停止位来识别字符时正在进行传输还是传输结束。 2.同步通信方式的特点:进行数据传输时,发送和接收双方要保持完全的同步,因此,要求接收和发送设备必须使用同一时钟。优点是可以实现高速度、大容量的数据传送;缺点是要求发生时钟和接收时钟保持严格同步,同时硬件复杂。可以这样说,不管是异步通信还是同步通信都需要进行同步,只是异步通信通过传送字符内的起始位来进行同步,而同步通信采用共用外部时钟来进行同步。所以,可以说前者是自同步,后者是外同步。---------------------------- 同步通信原理 同步通信是一种连续串行传送数据的通信方式,一次通信只传送一帧信息。这里的信息帧与异步通信中的字符帧不

同,通常含有若干个数据字符。 采用同步通信时,将许多字符组成一个信息组,这样,字符可以一个接一个地传输,但是,在每组信息(通常称为帧)的开始要加上同步字符,在没有信息要传输时,要填上空字符,因为同步传输不允许有间隙。在同步传输过程中,一个字符可以对应5~8位。当然,对同一个传输过程,所 有字符对应同样的数位,比如说n位。这样,传输时,按每n位划分为一个时间片,发送端在一个时间片中发送一个字符,接收端则在一个时间片中接收一个字符。 同步传输时,一个信息帧中包含许多字符,每个信息帧用同步字符作为开始,一般将同步字符和空字符用同一个代码。在整个系统中,由一个统一的时钟控制发送端的发送和空字符用同一个代码。接收端当然是应该能识别同步字符的,当检测到有一串数位和同步字符相匹配时,就认为开始一个信息帧,于是,把此后的数位作为实际传输信息来处理。 异步通信原理 异步通信是一种很常用的通信方式。异步通信在发送字符时,所发送的字符之间的时间间隔可以是任意的。当然,

jQuery调用AJAX异步操作超清晰教程

JQUERY AJAX异步操作详细说明 AJAX 全称 Asynchronous JavaScript and XML(异步的 JavaScript 和XML)。它并非一种新的技术,而是以下几种原有技术的结合体。 1)使用CSS和XHTML来表示。 2)使用DOM模型来交互和动态显示。 3)使用XMLHttpRequest来和服务器进行异步通信。 4)使用javascript来绑定和调用。 通过AJAX异步技术,可以在客户端脚本与web服务器交互数据的过程中使用XMLHttpRequest对象来完成HTTP请求(Request)/应答(Response)模型: 1)不需要用户等待服务端响应。在异步派发XMLHttpRequest请求后控制 权马上就被返回到浏览器。界面不会出现白板,在得到服务器响应之前 还可以友好的给出一个加载提示。 2)不需要重新加载整个页面。为XMLHttpRequest注册一个回调函数,待 服务器响应到达时,触发回调函数,并且传递所需的少量数据。“按需 取数据”也降低了服务器的压力。 3)不需要使用隐藏或内嵌的框架。在XHR对象之前,模拟Ajax通信通常 使用hack手段,如使用隐藏的或内嵌的框架(