SAA8122A中文资料
SAA8122A
Digital Still Camera Processor (ImagIC family)
Rev. 01 — 20 April 2000
Objective speci?cation
c
c
1.Description
The DSC SAA8122A is a high performance, low power, single-chip Million
Instructions Per Second (MIPS) based signal processor, part of the ImagIC family,which is dedicated to image processing, compression, formatting and storage. The DSC SAA8122A is optimized for use with Philips range of CCDs (e.g: FXA1022,2Mpixels CCD), V-driver (TDA9991), CDS/PGA/ADC (TDA9952), allowing easy implementation of a complete system solution and fast development of high performance consumer digital still cameras.
The SAA8122A is designed as a single-chip device, able to perform all treatments and connections required for a wide range of Digital Still Cameras. Its embedded RISC CPU, for which the development environment is available, enables shorter development and validation cycles, as well as faster feature upgrade. Since one of the main objectives of the SAA8122A is addressing a wide range of CCD sensors, a DSP (with advanced embedded algorithm)for camera signal processing is integrated with a high level of programmability for pulses generation.
The JPEG core is hardware based in order to allow high-speed image data compression.
2.Features
2.1General
s Supports a wide range of progressive CCDs (VGA, SVGA, QGA, XGA, EQGA),with RGB Bayer ?lters up to 2Mpixels
s Performs an advanced RGB to YUV conversion
s Includes a smart measurement unit to speed up the control loop (focus,auto white balance, etc.)
s Supports a wide range of LCD and TV formats (both NTSC and PAL) with text insertion features
s Includes an embedded JPEG encoder/decoder unit
s Includes a MIPS PR3001 CPU, running at a frequency in a range from 12to 28MHz
s PRISC compatible PI-bus architecture, interrupt, power management, clock and reset architectures
s Includes a dedicated video bus supporting SDRAM memory for picture storage
s Interface to ROM,DRAM,SRAM,?ash and PC Card[Compact Flash and SSFDC (SmartMedia)]
s Integrated general purpose peripheral units like a UART, timers, an I2C-bus transceiver, ADC converters, RTC and I/O ports
s Includes USB and RS-232C communication interfaces.
2.2External interfaces
s Two UART (RS-232) data ports with DMA capabilities (≤187.5kbit/s) including hardware ?ow control RxD, TxD, RTS, CTS for modem support
s32general purpose, bidirectional I/O interface pins, the ?rst 8bits may also be used as interrupt inputs
s T wo PWM outputs (8-bit resolution).
2.3CPU related features
s32-bit PR3001 core
s1-kbyte data cache and 4-kbyte instruction cache
s Programmable low-power mode, including wake-up on interrupt
s Memory management unit [Translation Lookaside Buffer (TLB)]
s Two built in 24-bit general purpose timers and one 24-bit watchdog timer
s Real-time clock unit (active in sleep mode)
s On-chip 8-kbyte SRAM for storing code which needs fast execution
s Platform software based on real-time pSOS (plug-in Silicon Operating System).
2.4DSP features
s Advanced colour reconstruction
s Programmable digital ?lters for noise reduction and contour enhancement
s16programmable measurement windows allowing to perform the measurements necessary for exposure, white balance and focus adjustment in a DSC system;
available measurement outputs for exposure, white balance and focus control.
2.5Pulse pattern generator features
s Programmable through dedicated PC-software, allowing to drive all CCDs currently present in the market, as well as CDS/AGC/ADC chips: up to
8×8kpixels.
2.6JPEG
s Fully ISO10918 compliant
s Supports Tiff, Exif 2.1, DCF & DPOF
s Quick compression (4images/s for a 1.3Mpixels resolution).
2.7USB interface
s Fully compatible with USB.
2.8Card interfaces
s Compatible with all SSFDC/CF cards on the market.
2.9Bus
s Bus structure allows for parallel processing depending on software implementation, allowing easy system optimization.
2.10SDRAM interface features
s Supports up to 128Mbyte of SDRAM and 16-bit wide addressses s Bus speed: 1or 2times CCD pixel clock s 32-bit bus width.
3.Quick reference data
[1]The supplies considered as digital supply (V DDD ) are: V DDD , V DDD(RTC).
[2]The supplies considered as analog supply (V DDA ) are: V DDA(SPLL), V DDA(PLL), V DDA(BG), V DDA(PPG1),V DDA(ADC), V DDA(OUTPUT1), V DDA(OUTPUT2), V DDA(LCDR), V DDA(LCDG), V DDA(LCDB), V DDA(DLL).[3]
Including voltage on outputs in 3-state mode; only valid when supply voltage is present.
4.Ordering information
Table 1:Quick reference data Symbol Parameter
Conditions
Min Typ Max Unit V DDD digital supply voltage [1]3 3.3 3.6V V DDA analog supply current [2]
3 3.3 3.6V I P total supply current f clk =25MHz
?360560mA V I
input voltage general
0?V DDD V 5V tolerant cells only
[3]
0? 5.5V V O output voltage output active
0?V DDD V T amb ambient temperature 02570°C f clk
clock frequency
?
25
27
MHz
Table 2:
Ordering information
Type number
Package Name
Description
Version SAA8122AEL
LFBGA324
plastic low pro?le ?ne-pitch ball grid array package; 324balls;body 16×16×1.2mm
SOT571-1
6.Pinning information
6.1Pinning
6.2Pin description
Fig 2.System block diagram.
handbook, full pagewidth
FCE687
SAA8122A
TDA9952CCD FXA1022
lens
V-DRIVER TDA9991
10
to LCD to TV
to cards (SSFDC, CF)
USB IRDA to PC
Fig 3.Pin con?guration (bottom view).
handbook, halfpage
FCE677
A
B C D E F H K G J L M N P R T U V 24681012141618
1
357911131517SAA8122AEL
Table 3:Pin description
Symbol Pin Type Description V DDD A1-digital supply voltage
V SSA(DLL)A2-analog ground for DLL of PPG V DDA(DLL)A3-analog supply voltage for DLL of PPG DISP_VSYNC A4O digital vertical synchronization signal IO1/IRQ17A5I/O I/O port 0 bit 1 or interrupt request 17V DDA(LCDG)A6P analog supply voltage for DAC component G
Table 3:Pin description…continued
Symbol Pin Type Description
CREF_BG1A8-band-gap1
V SS(BG)A9P ground for BG of video DAC
SYSRSTIN A10I system reset input/output; active LOW
V SS(RTC)A11P ground for RTC
T0_CAP0A12I timer0 capture input0
CNT2A13I timer2 count pulse input
CNT1A14I timer1 count pulse input
PWM0A15O timer0 PWM output
ADC0A16I analog input signal0 for level measurement ADC3A17I analog input signal3 for level measurement V SS(ADC)A18P ground for ADC
ANPPG1B1O PPG analog signal1
IO6/IRQ22B4I/O I/O port0 bit6 or interrupt request22
IO3/IRQ19B5I/O I/O port0 bit3 or interrupt request19
LCD_G B6O analog green signal
VIDEO_OUT2B7O video output signal2
V SSA(ref)B8O analog reference ground
SC_TCK B9I test clock input for surround scan chains TCK B10I test clock input
XT ALCCDIN B11-oscillator input from a speci?c CCD crystal
V DDA(SPLL)B12P analog supply voltage for SPLL
V SS(PLL)B13P ground for PLL
CNT0B14I timer0 count pulse input
V SSA(ref)(ADC)B15O analog reference ground for ADC
ADC2B16I analog input signal2 for level measurement V DDA(ADC)B17P analog supply voltage for ADC
IO23B18I/O I/O port2 bit7
V DDA(PPG1)C1P analog supply voltage for PPG
V DDA(PPG0)C2P analog supply voltage for PPG
V DDA(DLL)C3P analog supply voltage for DLL of PPG
IO7/IRQ23C4I/O I/O port0 bit7 or interrupt request23
IO4/IRQ20C5I/O I/O port0 bit4 or interrupt request20
LCD_R C6O analog red signal
LCD_B C7O analog blue signal
V DDA(OUTPUT1)C8P analog supply voltage for DAC video output1 V DDA(BG)C9P analog supply voltage for BG of video DAC TMS C10I test mode select input
XT AL32KIN C11-oscillator input from a 32kHz crystal
XT AL10IN C12-oscillator input from a 10MHz crystal
GA TE2C13I timer2 gate input
Table 3:Pin description…continued
Symbol Pin Type Description
PWM1C15O timer1 PWM output
ADC1C16I analog input signal1 for level measurement IO22C17I/O I/O port2 bit6
IO16C18I/O I/O port2 bit0
ANPPG7D1O PPG analog signal7
V SSA(PPG1)D2P analog ground for PPG
DISP_HSYNC D3O digital horizontal synchronization signal
IO5/IRQ21D4I/O I/O port0 bit5 or interrupt request21
IO0/IRQ16D5I/O I/O port0 bit0 or interrupt request16
V SSA(LCD)D6P analog ground for display RGB
V SS(OUTPUT)D7P ground for DAC video output
CREF_BG2D8-band-gap2
TDO D9O test data output
TDI D10I test data input
XT AL32KOUT D11-oscillator output from a 32kHz crystal
XT AL10OUT D12-oscillator output from a 10MHz crystal
T0_CAP1D13I timer0 capture input1
GA TE0D14I timer0 gate input
PWM2D15O timer2 PWM output
IO17D16I/O I/O port2 bit1
IO15D17I/O I/O port1 bit7
IO11D18I/O I/O port1 bit3
PPG1E1O PPG digital signal0
PPG2E2O PPG digital signal1
ANPPG8E3O PPG analog signal8
V DDA(PPG0)E4P analog supply voltage for PPG
IO2/IRQ18E5I/O I/O port0 bit2 or interrupt request18
V DDA(LCDR)E6P analog supply voltage for DAC component R V DDA(LCDB)E7P analog supply voltage for DAC component B VIDEO_OUT1E8O video output signal1
SYSRST E9O system reset output; active LOW
TRST E10I test reset input
V DDD(RTC)E11P digital supply voltage for RTC
XT ALCCDOUT E12-oscillator output from a speci?c CCD crystal GA TE1E14I timer1 gate input
IO18E15I/O I/O port2 bit2
IO10E16I/O I/O port1 bit2
IO9E17I/O I/O port1 bit1
UA_CLK E18I UART external clock
PPG5F1O PPG digital signal4
Table 3:Pin description…continued
Symbol Pin Type Description
PPG3F3O PPG digital signal2
ANPPG5F4O PPG analog signal5
ANPPG3F5O PPG analog signal3
V SS F6-ground
V SS F7-ground
V DD F8-supply voltage
V DD F9-supply voltage
V DD F10-supply voltage
V DD F11-supply voltage
V DD F12-supply voltage
IO20F13I/O I/O port2 bit4
IO19F14I/O I/O port2 bit3
IO12F15I/O I/O port1 bit4
CTS F16I UART clear to send
RXD F17I UART receive input
TXD F18O UART transmit output
PPG10G1O PPG digital signal17
PPG12G2O PPG digital control signal1
PPG8G3O PPG digital signal8
PPG4G4O PPG digital signal3
ANPPG6G5O PPG analog signal6
ANPPG2G6O PPG analog signal2
V DD G7-supply voltage
V SS G8-ground
V SS G9-ground
V SS G10-ground
V SS G11-ground
V DD G12-supply voltage
IO21G13I/O I/O port2 bit5
IO13G14I/O I/O port1 bit5
RTS G15O UART request to send
SDA G16I/O I2C-bus data
SCL G17I/O I2C-bus clock
n.c.G18-not connected
HDHREF H1I/O PPG horizontal synchronization signal VDVS H2I/O PPG vertical synchronization signal PPG13H3O PPG digital control signal2
PPG7H4O PPG digital control signal6
PPG14H5O PPG digital control signal3
ANPPG4H6O PPG analog signal4
Table 3:Pin description…continued
Symbol Pin Type Description
V SS H8-ground
V SS H9-ground
V SS H10-ground
V SS H11-ground
V DD H12-supply voltage
IO14H13I/O I/O port1 bit6 RXVPI H14I USB
n.c.H15-not connected RXVMI H16I/O USB
TXVPO H17O USB
RXDAT A H18I USB
CCD_IM2J1I digital image signal2 CCD_IM3J2I digital image signal3 CCD_IM4J3I digital image signal4 PPG11J4O PPG digital signal18 PPG9J5O PPG digital signal8
V DD J6-supply voltage
V DD J7-supply voltage
V SS J8-ground
V SS J9-ground
V SS J10-ground
V SS J11-ground
V DD J12-supply voltage
IO8J13I/O I/O port1 bit0 SUSPEND J14O USB
TXOE J15O USB
D2J16I/O EBIU D2
D3J17I/O EBIU D3
D0J18I/O EBIU D0
CCD_IM10K1I digital image signal10 CCD_IM9K2I digital image signal9 CCD_IM8K3I digital image signal8 CCD_IM1K4I digital image signal1 CCD_IM0K5I digital image signal0 V DD K6-supply voltage
V DD K7-supply voltage
V SS K8-ground
V SS K9-ground
V SS K10-ground
V SS K11-ground
Table 3:Pin description…continued
Symbol Pin Type Description
TXVMO K13O USB
D1K14I/O EBIU D1
D4K15I/O EBIU D4
D6K16I/O EBIU D6
D7K17I/O EBIU D7
D8K18I/O EBIU D8
SD_A[0]L1O SDRAM controller address bus bit0
SD_A[3]L2O SDRAM controller address bus bit3
SD_A[2]L3O SDRAM controller address bus bit2
CCD_IM6L4I digital image signal6
CCD_IM7L5I digital image signal7
CCD_IM5L6I digital image signal5
V DD L7-supply voltage
V SS L8-ground
V SS L9-ground
V SS L10-ground
V SS L11-ground
V DD L12-supply voltage
D5L13I/O EBIU D5
D9L14I/O EBIU D9
D11L15I/O EBIU D11
D14L16I/O EBIU D14
D13L17I/O EBIU D13
D12L18I/O EBIU D12
SD_A[7]M1O SDRAM controller address bus bit7
SD_A[8]M2O SDRAM controller address bus bit8
SD_A[9]M3O SDRAM controller address bus bit9
SD_A[4]M4O SDRAM controller address bus bit4
SD_A[1]M5O SDRAM controller address bus bit1
CCD_IM11M6I digital image signal11
V DD M7-supply voltage
V SS M8-ground
V SS M9-ground
V SS M10-ground
V SS M11-ground
V DD M12-supply voltage
D10M13I/O EBIU D10
SC_SE M14O EBIU controller SE signal for SSFDC card; active LOW D15M15I/O EBIU D15
PC_WAIT2M16I EBIU controller WAIT signal for PC card2; active LOW
Table 3:Pin description…continued
Symbol Pin Type Description
SC_CLE M18O EBIU controller CLE signal for SSFDC card
SD_A[12]N1O SDRAM controller address bus bit12
SD_A[13]N2O SDRAM controller address bus bit13
SD_A[14]N3O SDRAM controller address bus bit14
SD_A[10]N4O SDRAM controller address bus bit10
SD_A[6]N5O SDRAM controller address bus bit6
SD_A[5]N6O SDRAM controller address bus bit5
V DD N7-supply voltage
V DD N8-supply voltage
V DD N9-supply voltage
V DD N10-supply voltage
V DD N11-supply voltage
SC_ALE N12O EBIU controller ALE signal for SSFDC card
PC2_CE1N13O EBIU controller CE1 signal for PC card2; active LOW
PC2_CE2N14O EBIU controller CE2 signal for PC card2; active LOW
PC_REG N15O EBIU controller REG signal for PC cards; active LOW
PC_WAIT1N16O EBIU controller WAIT signal for PC card1; active LOW
IOWR_WE N17O EBIU controller IORD signal for PC cards; active LOW
IORD_RE N18O EBIU controller IORD signal for PC cards; active LOW
SD_CLKOUT P1O SDRAM controller clock output
SD_CLKIN P2I SDRAM controller clock input
SD_CS2P3O SDRAM controller chip select for memory2; active LOW
SD_CLKEN P4O SDRAM controller clock enable
SD_A[11]P5O SDRAM controller address bus bit11
V DD P6-supply voltage
SD_D[7]P7I/O SDRAM controller data bus bit7
IO25P8I/O I/O port3 bit1
IO38P9I/O I/O port4 bit6
A25P10I/O EBIU A25 (Strapin[0] during boot sequence)
A21P11I/O EBIU A21 (Strapin[4] during boot sequence)
V DD P12-supply voltage
A14P13I/O EBIU A14
SCLK P14O EBIU controller clock signal for external peripherals
A9P15I/O EBIU A9
CAS0P16O EBIU controller CAS signal for DRAM memory for lower byte; used as data
strobe signal for lower byte for general chip select; active LOW
PC1_CE1P17O EBIU controller CE1 signal for PC card1; active LOW
PC1_CE2P18O EBIU controller CE2 signal for PC card1; active LOW
SD_CS0R1O SDRAM controller chip select for memory0; active LOW
SD_CS1R2O SDRAM controller chip select for memory1; active LOW
Table 3:Pin description…continued
Symbol Pin Type Description
SD_D[4]R4I/O SDRAM controller data bus bit4
SD_RAS R5O SDRAM controller row address strobe; active LOW
SD_D[6]R6I/O SDRAM controller data bus bit6
SD_D[13]R7I/O SDRAM controller data bus bit13
IO30R8I/O I/O port3 bit6
IO37R9I/O I/O port4 bit5
A24R10I/O EBIU A24 (Strapin[1] during boot sequence)
A19R11I/O EBIU A19 (Strapin[6] and Strapin[9] during boot sequence)
A18R12I/O EBIU A18 (Strapin[10] during boot sequence)
A13R13I/O EBIU A13
A5R14O EBIU A5
CS6R15O EBIU controller chip select6; active LOW
CAS1R16O EBIU controller CAS signal for DRAM memory for upper byte; used as data
strobe signal for upper byte for general chip select; active LOW
OE R17O EBIU controller output enable signal; active LOW
RAS R18O EBIU controller RAS signal for DRAM memory; active LOW
SD_CAS T1O SDRAM controller column address strobe; active LOW
SD_WE T2O SDRAM controller write enable; active LOW
SD_D[3]T3I/O SDRAM controller data bus bit3
SD_D[8]T4I/O SDRAM controller data bus bit8
SD_D[10]T5I/O SDRAM controller data bus bit10
SD_D[14]T6I/O SDRAM controller data bus bit14
IO26T7I/O I/O port3 bit2
IO29T8I/O I/O port3 bit5
IO33T9I/O I/O port4 bit1
IO36T10I/O I/O port4 bit4
A23T11I/O EBIU A23 (Strapin[2] during boot sequence)
A16T12I/O EBIU A16
A12T13I/O EBIU A12
A3T14O EBIU A3
CS7T15O EBIU controller chip select7; active LOW
CS4T16O EBIU controller chip select4; active LOW
WE T17O EBIU controller write enable signal; active LOW
CS_WAIT T18O EBIU controller wait signal for chip selects; active LOW
SD_DQM0U1O SDRAM controller DQ mask enable for byte0; active LOW
SD_DQM1U2O SDRAM controller DQ mask enable for byte1; active LOW
SD_D[2]U3I/O SDRAM controller data bus bit2
SD_D[9]U4I/O SDRAM controller data bus bit9
SD_D[11]U5I/O SDRAM controller data bus bit11
SD_D[15]U6I/O SDRAM controller data bus bit15
Table 3:Pin description…continued
Symbol Pin Type Description
IO32U8I/O I/O port4 bit0
IO34U9I/O I/O port4 bit2
A22U10I/O EBIU A22 (Strapin[3] during boot sequence)
A17U11I/O EBIU A17 (Strapin[11] during boot sequence)
A11U12I/O EBIU A11
A8U13I/O EBIU A8
A4U14O EBIU A4
A2U15O EBIU A2
CS5U16O EBIU controller chip select5; active LOW
CS3U17O EBIU controller chip select3; active LOW
CS0U18O EBIU controller chip select0; active LOW
SD_D[0]V1I/O SDRAM controller data bus bit0
SD_D[1]V2I/O SDRAM controller data bus bit1
SD_D[5]V3I/O SDRAM controller data bus bit5
SD_D[12]V4I/O SDRAM controller data bus bit12
IO24V5I/O I/O port3 bit0
IO28V6I/O I/O port3 bit4
IO31V7I/O I/O port3 bit7
IO35V8I/O I/O port4 bit3
IO39V9I/O I/O port4 bit7
A20V10I/O EBIU A20 (Strapin[5] and Strapin[8] during boot sequence) A15V11I/O EBIU A15
A10V12I/O EBIU A10
A7V13I/O EBIU A7
A6V14I/O EBIU A6
A1V15O EBIU A1
A0V16O EBIU A0
CS2V17O EBIU controller chip select2; active LOW
CS1V18O EBIU controller chip select1; active LOW
7.Limiting values
[1]Value may not exceed 4V .
[2]Including voltage on outputs in 3-state mode.[3]Only valid when supply voltage is present.
[4]The peak current is limited to 10times the corresponding maximum current.[5]
Dependent of package and not yet determined.
8.Characteristics
[1]
V DDD(RTC) is the single supply which may be on when the others are off. In this case the I/Os of the SAA8122A have to be at 0V .
Table 4:Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).Symbol Parameter
Conditions Min Max Unit V DDD digital supply voltage ?0.54V V DDA analog supply voltage ?0.54
V
V I
DC input voltage
general [1][2]?0.5V DD +0.5V 5V tolerant cells only
[2][3]?0.5?0.5V I DD DC supply current per supply pin
[4]
?60mA I SS DC ground current per ground pin
[4]
?60mA T stg
storage temperature
[5]
125
°C
Table 5:General supply characteristics
Symbol Parameter
Conditions
Min Typ Max Unit V DDD digital supply voltage 3.0 3.3 3.6V V DDA(DLL)analog supply voltage for DLL
3.0 3.3 3.6V V DDA(LCDR)analog supply voltage for LCDR output of DAC 3.0 3.3 3.6V V DDA(LCDG)analog supply voltage for LCDG output of DAC 3.0 3.3 3.6V V DDA(LCDB)
analog supply voltage for LCDB
3.0 3.3 3.6V V DDA(OUTPUT1)analog supply voltage for video output 1 of DAC 3.0 3.3 3.6V V DDA(OUTPUT2)analog supply voltage for video output 2 of DAC 3.0 3.3 3.6V V DDA(ADC)analog supply voltage for ADC 3.0 3.3 3.6V V DDA(PPG1)analog supply voltage for PPG 3.0 3.3 3.6V V DDA(PPG0)analog supply voltage for PPG 3.0 3.3 3.6V V DDA(BG)analog supply voltage for bandgap 3.0 3.3 3.6V V DDA(PLL)analog supply voltage for PLL 3.0 3.3 3.6V V DDA(SPLL)analog supply voltage for SPLL 3.0
3.3 3.6V V DDD(RTC)
digital supply voltage for RTC
[1]
3.0
3.3
3.6
V
Table 6:Operating characteristics
Symbol Parameter Conditions Min Typ Max Unit
3.0 3.3 3.6V
V DDA(LCDR)analog supply voltage for LCDR
output of DAC
V DDA(LCDG)analog supply voltage for LCDG
3.0 3.3 3.6V
output of DAC
V DDA(LCDB)analog supply voltage for LCDB
3.0 3.3 3.6V
output of DAC
3.0 3.3 3.6V
V DDA(OUTPUT1)analog supply voltage for video
output1 of DAC
V DDA(OUTPUT2)analog supply voltage for video
3.0 3.3 3.6V
output2 of DAC
V DDA(BG)analog supply voltage for bandgap 3.0 3.3 3.6V
V BG bandgap reference voltage(4σ) 1.18 1.22 1.26V
V OL LOW-level output voltage code 0-0.225-V
V OH HIGH-level output voltage code 511- 1.625-V LCD channels (1k? buffer)
R L load resistance-1-k?C L load capacitance--5pF RES resolution-8-bit LCD channels (75? mode)
R L load resistance-75-?
C L load capacitance-5100pF RES resolution-9-bit VIDEO_OUT channels (1k? buffer)
R L load resistance-1-k?C L load capacitance--5pF RES resolution-8-bit VIDEO_OUT channels (1k? mode)
R L load resistance-1-k?C L load capacitance--5pF RES resolution-9-bit ADC
3.0 3.3 3.6V
V DDA(ADC)analog supply voltage for analog
ADC
?V DD supply voltage difference between
--0.2V V DDA and V DDA(ADC)
RES resolution8-10bit C i input capacitance-2-pF V i input voltage0- 3.3V
f sample sample frequency8-bit0-100kHz PLL
3.0 3.3 3.6V
V DDA(PLL)analog supply voltage for analog
PLL
?V DD supply voltage difference between V DDA and V DDA(PLL)--0.2V f clk clock frequency
-96-MHz SPLL V DDA(SPLL)analog supply voltage for analog SPLL
3.0 3.3 3.6V ?V DD
supply voltage difference between V DDA and V DDA(SPLL)--0.2
V
Power-on reset V trip trip level of power-on reset 1.5 2.07 2.65V t HIGH
time that V DDA has to be above 2.65V before internal reset signal is asserted
--2
μs
t LOW
time that V DDA has to be above 2.65V before internal reset signal is de-asserted
--8μs
Analog PPG V DDA(DLL)
analog supply voltage for analog DLL
3.0 3.3 3.6V ?V DD-DDA(DLL)supply voltage difference between
V DDA and V DDA(DLL)--0.2V V DDA(PPG1);V DDA(PPG0)
analog supply voltage for analog PPG
3.0 3.3 3.6V ?V DD-DDA(PPG)supply voltage difference between
V DDA and V DDA(PPG1) or V DDA(PPG0)--0.2
V
I/Os (V DDD =V DDA, T amb =0to 60°C)Data and control inputs
SD_CLKIN V IL LOW-level digital input voltage 0-0.3V DDD V V IH HIGH-level digital input voltage 0.7V DDD -V DDD V C i input capacitance - 1.14-pF I IL LOW-level input current V I =0V --1μA I IH HIGH-level input current V I =V DDD
--1μA I lu(I/O)
I/O latch-up current
?0.5 100 --mA CS_WAIT,PC_WAIT1,PC_WAIT2, SC_TCK, TCK, TDI, TMS, TRST, CCD_IM0to CCD_IM11, CNT0to CNT2,GATE0to GATE2, T0_CAP0, T0_CAP1, CTS, RXD, UA_CLK, RXDATA, RXVMI, RXVPI V IL LOW-level digital input voltage 0-0.8V V IH HIGH-level digital input voltage 2.0- 5.5V C i input capacitance - 1.2-pF I IL LOW-level input current V I =0V --1μA I IH HIGH-level input current V I =V DDD --1μA I lu(I/O) I/O latch-up current ?0.5 100--mA SYSRSTIN Table 6:Operating characteristics …continued Symbol Parameter Conditions Min Typ Max Unit V IH HIGH-level digital input voltage 2.0- 5.5V V hys hysteresis voltage0.4--V C i input capacitance- 1.2-pF I IL LOW-level input current V I=0V--1μA I IH HIGH-level input current V I=V DDD--1μA I lu(I/O)I/O latch-up current?0.5 ANPPG1to ANPPG8 V OL LOW-level digital output voltage I OL=4mA0-0.4V V OH HIGH-level digital output voltage I OH=4mA V DDA?0.4-V DDA V C o(L)(max)maximum output load capacitance[1]--100pF I OL LOW-level output current V OL=0.4V; V OH=V DDA?0.4 4--mA I OH HIGH-level output current V OH=V DDA?0.4?4--mA SCLK, SD_A[0]to SD_A[14],SD_CAS, SD_CLKEN, SD_CLKOUT,SD_CS0to SD_CS3,SD_DQM0to SD_DQM1, SD_RAS,SD_WE V OL LOW-level digital output voltage I OL=4mA0-0.4V V OH HIGH-level digital output voltage I OH=?4mA V DDD?0.4V DDD V C i input capacitance--1-pF C o(L)(max)maximum output load capacitance-[1]--100pF I OL LOW-level output current V OL=0.4V---μA I OH HIGH-level output current V OH=V DDD?0.4?4--mA I OZ3-state output leakage current V O=0; V O=V DDD --1μA TDO,SYSRST, PWM0to PWM2, RTS, TXD, SUSPEND, TXOE, TXVMO, TXVPO, DISP_HSYNC, DISP_VSYNC V OL LOW-level digital output voltage I OL=2mA0-0.4V V OH HIGH-level digital output voltage I OH=?2mA V DDD?0.4-V DDD V C i input capacitance-- 2.2-pF C o(L)(max)maximum output load capacitance-[1]--30pF I OL LOW-level output current V OL=0.4V; V OH=V DDD?0.4 2--mA I OH HIGH-level output current V OH=V DDD?0.4?2--mA I OZ3-state output leakage current V O=0; V O=V DD --1μA CAS0,CAS1,CS0to CS7,IORD_RE,IOWR_WE,OE,PC_REG,PC1_CE1,PC1_CE2,RAS, SC_ALE,SC_SE,WE, PPG1to PPG14 V OL LOW-level digital output voltage I OL=4mA0-0.4V V OH HIGH-level digital output voltage I OH=?4mA V DDD?0.4-V DDD V C i input capacitance-- 2.4-pF C o(L)(max)maximum output load capacitance-[1]--30pF I OL LOW-level output current V OL=0.4V; V OH=V DDD?0.44--mA Table 6:Operating characteristics…continued Symbol Parameter Conditions Min Typ Max Unit I OZ 3-state output leakage current V O =0;V O =V DDD --1 μA Data and control I/Os SD_D[0]to SD_D[15]V IL LOW-level digital input voltage -0-0.3V DDD V V IH HIGH-level digital input voltage -0.7V DDD -V DDD V V OL LOW-level digital output voltage I OL =4mA 0-0.4V V OH HIGH-level digital output voltage I OH =?4mA V DDD ?0.4- V DDD V C i input capacitance -- 1.2-pF C o(L)(max)maximum output load capacitance -[1] --100pF I OL LOW-level output current V OL =0.4V; V OH =V DDD ?0.44--mA I OH HIGH-level output current V OH =V DDD ?0.4?4--mA I OZ 3-state output leakage current V O =0;V O =V DDD --1μA I IL LOW-level input current V I =0--1μA I IH HIGH-level input current V I =V DDD --1μA A0to A15, IO8to IO15, HDHREF , VDVS V IL LOW-level digital input voltage -0-0.6V DDD V V IH HIGH-level digital input voltage -0.7V DDD -V DDD V V OL LOW-level digital output voltage I OL =4mA 0-0.4V V OH HIGH-level digital output voltage I OH =?4mA V DDD ?0.4- V DDD V C i input capacitance -- 2.5-pF C o(L)(max)maximum output load capacitance -[1]--30pF I OL LOW-level output current V OL =0.4V; V OH =V DDD ?0.44--mA I OH HIGH-level output current V OH =V DDD ?0.4?4--mA I OZ 3-state output leakage current V O =0;V O =V DDD --1μA I IL LOW-level input current V I =0--1μA I IH HIGH-level input current V I =V DDD --1μA IO16to IO23, IO0/IRQ16, IO1/IRQ17, IO2/IRQ18, IO3/IRQ19, IO4/IRQ20, IO5/IRQ21, IO6/IRQ22, IO7/IRQ23 V IL LOW-level digital input voltage -0-0.3V DDD V V IH HIGH-level digital input voltage -0.7V DDD -V DDD V V OL LOW-level digital output voltage I OL =2mA 0-0.4V V OH HIGH-level digital output voltage I OH =?2mA V DDD ?0.4- -V C i input capacitance -- 2.3-pF C o(L)(max)maximum output load capacitance ---30pF I OL LOW-level output current V OL =0.4V; V OH =V DDD ?0.42--mA I OH HIGH-level output current V OH =V DDD ?0.4 ?2 - - mA Table 6:Operating characteristics …continued Symbol Parameter Conditions Min Typ Max Unit I OZ 3-state output leakage current V O =0;V O =V DDD --1μA I IL LOW-level input current V I =0--1μA I IH HIGH-level input current V I =V DDD --1μA IO4to IO31V IL LOW-level digital input voltage -0-0.8V V IH HIGH-level digital input voltage - 2.0- 5.5V V OL LOW-level digital output voltage I OL =2mA --0.4V V OH HIGH-level digital output voltage I OH =?2mA V DDD ?0.4- V DDD V C i input capacitance -- 1.5-pF C o(L)(max)maximum output load capacitance ---30pF I OL LOW-level output current V OL =0.4V; V OH =V DDD ?0.42--mA I OH HIGH-level output current V OH =V DDD ?0.4?2--mA I OZ 3-state output leakage current V O =0;V O =V DDD --1μA I IL LOW-level input current V I =0--1μA I IH HIGH-level input current V I =V DDD --1μA IO32to IO39V IL LOW-level digital input voltage -0-0.8V V IH HIGH-level digital input voltage - 2.0- 5.5V V OL LOW-level digital output voltage I OL =1mA 0-0.4V V OH HIGH-level digital output voltage I OH =?1mA V DDD ?0.4- V DDD V C i input capacitance -- 1.4-pF C o(L)(max)maximum output load capacitance ---30pF I OL LOW-level output current V OL =0.4V; V OH =V DDD ?0.41--mA I OH HIGH-level output current V OH =V DDD ?0.4?1--mA I OZ 3-state output leakage current V O =0;V O =V DDD --1μA I IL LOW-level input current V I =0--1μA I IH HIGH-level input current V I =V DDD --1 μA I 2C-bus I/Os SCL and SDA V IL LOW-level digital input voltage -0-0.3V DDD V V IH HIGH-level digital input voltage -0-0.3V DDD V V hys hysteresis voltage -0.005V DDD - -V V OL LOW-level digital output voltage I OL =3mA --0.4V C i input capacitance -- 3.2-pF C o(L)(max) maximum output load capacitance -[1] - - 400 pF Table 6:Operating characteristics …continued Symbol Parameter Conditions Min Typ Max Unit [1] The maximum capacitance value given does not take into account the signal frequency. For critical signals the maximum capacitance has to be weighted according to the signal frequency and external devices constraints. I OZ 3-state output leakage V O =0;V O =V DDD --1μA I IL LOW-level input current V I =0--1μA I IH HIGH-level input current V I =V DDD --1 μA Table 6:Operating characteristics …continued Symbol Parameter Conditions Min Typ Max Unit