Comparison of measured and simulated characteristics of boron implanted 4H-SiC DiMOSFET

PROC. 25th INTERNATIONAL CONFERENCE ON MICROELECTRONICS (MIEL 2006), BELGRADE, SERBIA AND MONTENEGRO, 14-17 MAY, 2006 Comparison of measured and simulated characteristics of boron implanted 4H-SiC DiMOSFET

S. C. Kim, W. Bahng, K. H. Kim, I. H. Kang, S. J. Kim, N. K. Kim

Abstract – The vertical double implanted MOSFET (DiMOSFET) were fa bricated on 4H-SiC(0001) and the device characteristics were investigated. The sheet resistance of the Ni/Ti metals on the P-well region were 41.7k /? and 12.7k /? for post ion implantation annealed at 1600?and 1700?, respectively. The DiMOSFET device had blocking capability of 980V and the threshold voltage of 0.5V. Howeve r abnormal characteristics were observed in the forward characteristics. In this paper, we focused on the narrowing effect of JFET region due to lateral diffusion of implanted boron ions. The structures with narrow or closed JFET at the bottom region showed drain voltage shift.

I.I NTRODUCTION

Silicon carbide power devices have superior advantages compared to silicon power devices. SiC power devices are expected to be advantageous for saving energy consumption in electric power components. SiC MOSFET devices are very attractive devices for the high frequency and high power applications.

Among wide band-gap semiconductor materials, SiC hac the unique property that high quality thermal oxide can be easily grown. Furthermore, the high critical electric field (Ec) of SiC enables power MOSFETs using 10% drift layers thickness and 100 times the doping concentration as compared to silicon devices with comparable blocking voltage. This should result in a much smaller specific on-resistance R on,sp. Therefore, SiC MOSFET is regarded as a leading candidate for the next-generation ultra-low-loss power device [1]. A number of vertical high-voltage SiC MOSFETs has already been demonstrated [2, 3]. However, the performances of the present-time experimental SiC MOSFETs are far from reaching the theoretical limit. One of the serious problems in Si C-based vertical MOSFET is the poor channel mobility becau se of the large number of interface traps existing at the SiO2/SiC interface [4]. Much effort has been devoted to improve the SiC MOS channel mobility, but several difficulties still remain [5]. Generally, 4H-SiC is the preferred polytype since the bulk mobility is higher and more isotropic, compared to 6H-SiC. In this paper, characteristics of fabricated 4H-SiC MOSFET are presented, and compared to simulation results.

II.MOSFET F ABRICATION

The schematic diagram of fabricated 4H-SiC DiMOSFET is shown in Fig. 1. The DiMOSFET are made on 8r off axis Si face n+ substrates with 10? thick n-type epilayer with doping concentration of 3.36 10 cm-3. The p-well regions were made by six subsequent boron ion implantations at 650?with the acceleration energies ranged in the range 30keV – 370keV and implantation doses ranging between 5 1011cm-2– 2.08 1013cm-2 followed by post-implant activation for 30 min at 1600?in argon atmosphere. As a result, P-well was formed with a surface concentration and junction depth of around 5 1017 cm-3 and 0.65?. For ohmic contact with metal, the doping in the surface of p-well region was modified using three subsequent aluminum implantations at 650?using energies in the range 30keV – 140keV and implantation doses ranging between 1.5 1014cm-2– 5.0 1015cm-2. The final implantation depth and doping concentration are 0.2?and 5 1019cm-3, respectively. During high temperature activation, the surface was covered with a graphite cap layer in order to prevent sublimation and roughening of the

surface.

Fig. 1. Cross-section of simplified 4H-DiMOSFET.

For formation of deep p-well in the MOSFET, aluminum or boron implantation is generally used. Aluminum has a shallower acceptor level than boron and therefore its ionization is much higher and the resistance is

S. C. Kim, W. Bahng, K. H. Kim, I. H. Kang and N. K. Kim are with the Power Semiconductor Group, Korea Electrotechnology Research Institute, 28-1 Sungju-dong, Changwon-City, GyungNam, Rep. of Korea, E-mail: sckim@keri.re.kr S. J. Kim is with the R&D Depa rtment, Itswell Co., Ltd, 9-4BL, Ochang Scientific Industrial Complex, 1115-4 Namchon-ri,, Oksan-myeon, Cheongwon-gun, Chungbuk, Rep. of Korea, E-mail: kseongjin@https://www.360docs.net/doc/9914795846.html,

1-4244-0117-8/06/$20.00 ? 2006IEEE

much lower than boron at any given temperature [6].

However, aluminum ions are difficult to form deep p-well

due to its heavy mass. And heavy ions implantation causes

much damage in SiC lattice. Consequently, performance of

the devices would be degraded. From the above reason,

boron implantation was commonly used as a deep p-well

formation.

The source region was formed by nitrogen ion

implantation at 650?. Using multiple implant energies and

doses, a box profile of about 5u1019cm-3 and a junction 0.1?was fabricated. Thereafter a sacrificial oxide with thickness of 250 was grown in steam at 1100?and

removed in buffered HF solution. A PECVD oxide layer

(0.5?thick) was then deposited as an inter-metallic

dielectric layer, and the channel area was opened by wet

etching. The field oxide deposition temperature was 300?and deposition rate was 15nm/min, respectively. The gate oxide for the Si-face was then grown in 10 % N2O ambient in a oxidation furnace at a temperature of 1175? for one hour. The thickness of the gate oxide was measure to 20nm. A nickel and aluminum was used as the gate metal and nickel as the contact metal for source and drain. The field limiting ring (FLR) was fabricated for improve breakdown characteristics.

III.R ESULT AND D ISCUSSION

In the case of SiC devices, ohmic contact on the n-type substrate is relatively easy than on the p-type substrate. Therefore, many researchers would like to find different materials and different process for the ohmic contact. But this is obstacle for integration of the process in MOSFET. Accordingly, we measured the ohmic characteristics of Ni/Ti on the p-well formed aluminum implantation. To measure the specific resistance, we used linear and circular type TLM method. Fig. 2 shows the resistance characteristics of linear and circular pattern. From this figure, we find big difference depend on the annealed temperature between 1600?and 1700?. The transfer lengths were 2.6? in the 1600? annealed sample and 1.25?in the 1700?annealed sample, respectively. And also, the sheet resistances were 41.7k /?and 12.7k /?, respectively. From the above result, we calculated the N a-N d and activation ratios. The activation ratio of 1600 ? annealed sample was 10% and 60% for the 1700?annealed sample, respectively. And the specific contact resistance between Ni/Ti and p-well region were 1.8u10-5cm2 and 5.6u10-5cm2, respectively. Fig. 2. Measured result of resistance depends on the annealing temperatures.

Fig. 3 shows the room temperature on-state characteristics of 4H-SiC DiMOSFET. The channel with and length of this device are 660 and 5?, respectively. The threshold voltage extracted from saturation region is approximately 0.5V, which is significantly lower than the value reported up to now for the 1000V MOSFET devices. It was possible to low threshold voltage just using thin and high quality gate oxide layer. In the case of thin gate oxide, leakage current was increased through the thin gate oxide. And also, high voltage was applied to the source-drain and gate drain. Therefore, optimized termination structure is very important for the thin gate oxide. In this study, we optimized high voltage edge termination structure. The off-state characteristics are shown in Fig. 4. The device is normally-off, and showed stable avalanche behavior at a V DS of 980V.

Fig. 3. Forward characteristics of fabricated 4H-SiC DiMOSFET.

Fig. 4. Off-state characteristics of fabricated 4H-SiC power DiMOSFET.

The V DS/V th ratios of the fabricated 4H-SiC DiMOSFET are compared to those of published results in Table 1. From this table, most of the results of the V DS/V th are 100 to 400. I.e., high breakdown voltage causes the high threshold voltage in SiC MOSFET. However, V DS/V th ratio is 1960 in this study. This means that thin and high quality of gate oxide is very important factor for fabrication of SiC MOSFET.

T ABLE 1.

C OMPARISON OF V DS/V th RATIO IN THE PUBLISHE

D RESULT

V DS/V th ratio V th (V)

Breakdown

Voltage (V)

reference remark

- 4.6 ? Kiritani 4H-SiC

260 ~ 4303 ~ 5 1300 Banerjee

Lateral,

6H-SiC

140 ~ 1758 ~ 10 1400 Banerjee

Lateral,

6H-SiC

154 7.8 1200 Peters 4H-SiC 324 8.5 2750 Ryu 4H-SiC

267 3 800 Infineon

SIPMOS

Silicon

1960 0.5 980 This work 4H-SiC

One of the un-expected point is that there is no drain current until drain voltage is reached to 5V. To explain this result, simulation for the devices with several possible p-well structures using TCAD was done. In generally, the diffusion of boron ions along to the lateral direction is faster than along to surface normal direction due to the anisotropic nature of 4H-SiC during high temperature activation process [7]. In many reports, they considered that boron diffusion along to the lateral direction is just 1 ~ 2?. But, JFET region was almost closed in this study. Considering of our mask design, the distance of p-well was 10?. Therefore, the lateral diffusion length is almost 5?.From this reason, the electron passed the channel region could not flow to drain contact at the low source-drain

voltage. The considering DiMOSFET structure in the simulation is showed in Fig. 5. Because of retrograde doping profile, the concentration of the

implanted

ion of bottom side was higher than that of the surface. Therefore, diffused length in the bottom side of JFET was much longer than the surface. From this reason, the bottom of JFET region changed to intrinsic region. The simulation result of forward characteristics of considering structure is shown in Fig. 6. The dose dependencies of lateral diffusion during high temperature annealing were caused the JFET narrowing effect. This simulated forward characteristic was in good agreement with the measured one. As a result, current blocking layer was formed at the bottom side of JFET region due to lateral diffusion and retrograde doping profile of the boron ions. In generally, the diffusion of boron ions along to the lateral direction is faster than along to surface normal direction due to the anisotropic nature of 4H-SiC during high temperature activation process. But, the diffusion length to the lateral direction is much longer than we expected. Consequently, when we design and fabricate DiMOSFET using boron implantation, we have to consider lateral diffusion of boron ions.

Fig. 5. Conception view of lateral diffusion in the SiC DiMOSFET.

Fig. 6. Simulated forward characteristics of the considered DiMOSFET.

IV.S UMMARY

4H-SiC DiMOSFETs have been fabricated. The threshold voltage and avalanche breakdown voltage of the fabricated 4H-SiC DiMOSFET are 0.5V and 980V, respectively. However, abnormal forward characteristics of DiMOSFET devices have been observed because of the retrograde doping profiles in p-well region. To verify this result, we used the computer simulation. From the simulation result, current blocking layer was formed at the bottom side of JFET region due to lateral diffusion and retrograde doping profile of the boron ions. Consequently, when we design and fabricate 4H-SiC DiMOSFET using boron implantation, we have to consider lateral diffusion of boron ions.

A CKNOWLEDGEMENT

This work was done as a part of SiC Device Development Program (SICDDP) supported by MOCIE (Ministry of Commerce, Industry and Energy) Korea.

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