V50_Programming_Manual_MIXII

V50 IC Test System

MIX Programming Manual

Edition 1.3

May 2007

V50IC Test System MIX Programming Manual V1.3 Page: 1

Legal Notices

The Information Contained Herein is the Exclusive Property of Verigy Ltd and Shall not be Distributed, Reproduced, or Disclosed in Whole or in Part Without Prior Written Permission of Verigy Ltd.

Verigy Ltd. makes no warranty of any kind with regard to this document, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose.

Verigy Ltd. shall not be hold liable for errors contained herein or direct, indirect, special, incidental or consequential damages in connection with the furnishing, performance, or use of this document.

Verigy Ltd.5F-2, No. 25 Puding Road, Hsinchu, Taiwan

Copyright Notices. Copyright 2004 Verigy Ltd., all right reserved. Reproduction, adaptation, or translation of this document without prior written permission is prohibited, except as allowed under the copyright laws.

V50IC Test System MIX Programming Manual V1.3 Page: 2

Warranty

All Verigy Ltd instruments are warranted against defects in material and workmanship for a period of one year after date of shipment. Verigy Ltd agrees to repair or replace any assembly or component found to be defective, under normal use during this period.

Verigy Ltd.’s obligation under this warranty is limited solely to repairing any such instrument, which in Verigy Ltd’s sole opinion proves to be defective within the scope of the warranty when returned to the factory or to an authorized service center. Transportation to the factory or service center is to be prepaid by purchaser. Shipment should not be made without prior authorization by Verigy Ltd.

Verigy Ltd assumes no responsibility for its product being used in a hazardous or dangerous manner either alone or in conjunction with other equipment. High voltage/Current used in some instruments may be dangerous if misused. Special disclaimers apply to these instruments. Verigy Ltd assumes no liability for secondary charges or consequential damages and in any event, Verigy Ltd’s liability for breach of warranty under any contract or otherwise, shall not exceed the purchase price of the specific instrument shipped and against which a claim is made.

Any recommendations made by Verigy Ltd for use of its products are based upon tests believed to be reliable, but Verigy Ltd makes no warranty of the results to be obtained. This warranty is in lieu of all other warranties, expressed or implied, and no representative or person is authorized to represent or assume for Verigy Ltd any liability in connection with the sale of our products other than set forth herein.

This warranty does not apply to any products repaired or altered by persons not authorized by Verigy Ltd, or not in accordance with instructions furnished by Verigy Ltd. If the instrument is defective as a result of misuse, improper repair, or abnormal conditions or operations, repairs will be billed at cost.

Verigy Ltd

5F-2, No. 25 Puding Road, Hsinchu, Taiwan

TEL: 886-3-579-6220

FAX: 886-3-578-9989

V50IC Test System MIX Programming Manual V1.3 Page: 3

V50 IC Test System MIX Programming Manual

V1.3 Page: 4

Chapter 1 : Analog & Mixed-Signal Test Functions

1.1 : Block Diagram of Analog and Mixed-Signal Board

The Analog & Mixed-Signal Board consists of 9 types of resource.

(1). 3 sets of Arbitrary Waveform Generator (2). 1 set of Waveform Digitizer (3). 2 sets of Time Measurement Unit (4). 1 set of Data Acquisition (5). 8 sets of Voltage Reference Source (6). 1 set of Differential Voltage Meter (7). 1 set of Root Mean Square Meter (8). 8 sets of Voltage/Current Source/Meter (9). 32 Utility Relay driver

And, their specification are specified as below:

Arbitrary Waveform Generator

AWG Output Range Sample Rate Resolution

bits

±10V 500KSPS

16

Waveform Digitizer

Rate Resolution

DIG Input Range Sample

bits

16

±10V 500KSPS

Time Measurement Unit

TMU Input

Range Bandwidth Resolution

8.06nS

±10V 124MHz

Data Acquisition

Width

depth Mem.

DAQ Input Range Mem.

bits

±10V 128K 16

Voltage Reference Source

VRS Range Resolution

Accuracy

E:-15V~+40V 6.11mV ±0.5%±36.62mV

I:±15mA (max)

Differential Voltage Meter

Accuracy

DVM Range Resolution

E1:±100mV 3.0517uV ±0.5%±61.04uV

305.17uV ±0.5%±6.104mV

E2:±10V

Root Mean Square Meter

RMS Range Resolution

Accuracy

E1:1.4Vrms 21.36uVrms ±0.5%±128.17mVrms

E2:7.0Vrms 106.81uVrms ±0.5%±640.87mVrms

Voltage/Current Source/Meter (V/I Source/Meter)

Force

Accuracy

Range Resolution

E1: ±10V 1.22mV ±(0.03% of range + 0.03% of value)

2.44mV ±(0.03% of range + 0.03% of value)

E2:-15V~+20V

6.11mV ±(0.03% of range + 0.03% of value)

E3:-15V~+40V

46.38pA ±5nA

I1:±380nA

427.25pA ±(0.1% of range + 0.1% of value)

I2:±3.5uA

I3:±35.9uA 4.3823nA ±(0.1% of range + 0.1% of value)

43.823nA ±(0.1% of range + 0.1% of value)

I4:±359uA

427.25nA ±(0.1% of range + 0.1% of value)

I5:±3.5mA

3.9062uA ±(0.1% of range + 0.1% of value)

I6:±32mA

I7:±181mA 22.095uA ±(0.1% of range + 0.1% of value)

I8:±2A 244.14uA ±(0.2% of range + 0.2% of value)

Measure

V50IC Test System MIX Programming Manual V1.3 Page: 5

Range Resolution

Accuracy

305.17uV ±(0.015% of range + 0.015% of value) E1:±10V

610.35uV ±(0.015% of range + 0.015% of value) E2:-15V~+20V

1.5258mV ±(0.015% of range + 0.015% of value)

E3:-15V~+40V

11.596pA ±5nA

I1:±380nA

106.81pA ±(0.1% of range + 0.1% of value)

I2:±3.5uA

I3:±35.9uA 1.0956nA ±(0.1% of range + 0.1% of value)

I4:±359uA

10.956nA ±(0.1% of range + 0.1% of value)

106.81nA ±(0.1% of range + 0.1% of value)

I5:±3.5mA

976.56nA ±(0.1% of range + 0.1% of value)

I6:±32mA

I7:±181mA 5.5236uA ±(0.1% of range + 0.1% of value)

I8:±2A 61.035uA ±(0.2% of range + 0.2% of value)

Utility Relay

32 Utility relay.

Output Voltage 12V(Max)

Output Current 90mA(Max)

V50IC Test System MIX Programming Manual V1.3 Page: 6

2.1 : Function Calls

DSPII_SET_PLL_VALUE

SYNTAX:DSPII_SET_PLL_VALUE(source_name,N,M,L,L2); ARGUMENTS:

source_name : DSPII_AWGx, where x=1~24; DSPII_DIGx, where x=1~8; EXAMPLE:

DSPII_SET_PLL_VALUE(DSPII_AWG2, 100, 768, 750, 75); DESCRIPTION:

V50IC Test System MIX Programming Manual

DSPII_AWG_SETTING

SYNTAX:DSPII_AWG_SETTING(AWG_NO, Fcutoff, signal path select, output type select, PLL reference clock source select, AWG clock source select);

ARGUMENTS:

AWG_NO : 1~24

Fcutoff : ex. 3.5Hz or 1.1Khz or parameter name

Signal path select :

[PATH_SEL_DAC_OUTPUT]

[PATH_SEL_DAC_FILTER_OUTPUT]

[PATH_SEL_DAC_DIV8_FILTER_OUTPUT]

Output type select :

[OUTPUT_SEL_OFF]

[OUTPUT_SEL_DIFF]

[OUTPUT_SEL_SINGLE_END]

PLL reference clock source select :

[PLL_REF_SEL_10MHZ]

[PLL_REF_SEL_EXTERNAL]

AWG clock source select :

[SYNT_CLK_SEL_PLL]

[SYNT_CLK_SEL_DIRECT_SAMPLING]

[SYNT_CLK_SEL_AWG1_PLL]

EXAMPLE:

DSPII_AWG_SETTING(DSPII_AWG1,10khz,PATH_SEL_DAC_OUTPUT,OUTPUT_SEL_SINGLE_END, PLL_REF_SEL_10MHZ,SYNT_CLK_SEL_AWG1_PLL);

DESCRIPTION:

The Arbitrary Waveform Generator (AWG) is a programmable waveform generator. The AWG consists of a 128K deep waveform data storage memory, a phase-lock loop (PLL) for programmable clock generation, and high-speed digital-to-analog converter (DAC) with offset and gain control followed by a low-pass filter. The output of AWG can be programmed with either single-ended or differential types. The PLL of AWG1 provides a coherent clock source “AWG1_CLK” so that other resources such as AWG2, AWG3 and DIG can use this clock for coherent test.

V50IC Test System MIX Programming Manual

The AWG produces waveforms by reconstructing binary data that is stored in a 128K deep / 16 bits width waveform data storage memory. This stored data is presented to a 16 bits DAC at a programmed clock frequency (synthesized by PLL). The DAC produces a discreet DC voltage level for every binary code presented at its input. The DAC resolution is related to the number of its data bit inputs. A 16 bits DAC can support 65536 binary numbers or codes (0 to 65535). As an example, if the DAC has a full-scale output voltage swing from –10V to +10 V, then the resolution of its discreet DC output voltage levels (or “steps”) is as follows:

20V/65536 = 305uV

The main waveform DAC output is directly affected by two variables:

? the value of the binary code (amplitude) being input

? the rate (sampling frequency) at which the DAC is instructed to convert the binary code to a DC voltage

V50IC Test System MIX Programming Manual

V50 IC Test System MIX Programming Manual

SYNTAX:DSPII_AWG_START_SYNTHESIZE(AWG_NO, START_LABEL_NAME, END_LABEL_NAME,

loop_count);

ARGUMENTS:

AWG_NO : 1~24

START_LABEL_NAME : “FILENAME:LBELNAME” ;maximum 50 characters, extension name is unnecessary for the section of “FILENAME”.

END_LABEL_NAME : “FILENAME:LBELNAME” ;maximum 50 characters, extension name is unnecessary for the section of “FILENAME”.

loop_count : Loop count to generate waveform from “START_LABEL_NAME” to “END_LABEL_NAME”; 1~65535 is available, 65536 will enable a infinite loop.

EXAMPLE:

DSPII_AWG_START_SYNTHESIZE(1, tone:start_1k_1v, tone:end_1k_1v, 0x10000); DESCRIPTION:

As example, a waveform file is named “tone” . The AWG start synthesize from “atart_1k_1v”’ stop at label “end_1k_1v”.

An example of waveform file – “tone”

SYNTAX:DSPII_AWG_STOP_SYNTHESIZE(AWG_NO) ARGUMENTS:

AWG_NO : 1~24

EXAMPLE:

DSPII_AWG_STOP_SYNTHESIZE(DSPII_AWG1); DESCRIPTION: Stop AWG

V50IC Test System MIX Programming Manual

DSPII_DIG_SETTING

SYNTAX:DSPII_DIG_SETTING(DIG_NO, offset, Fcutoff, [RLY_ON], input mode select, signal path select, gain select, diagnostic path select, PLL reference clock select, Sample clock select); ARGUMENTS:

DIG_NO : 1~8

Offset : DC offset

Fcutoff : Cut-off frequency

[RLY_ON] : set DIG input relay on

input mode select :

[INPUT_MODE_DIFF]

[INPUT_MODE_SINGLE_END]

[INPUT_MODE_DIFF_50oHM]

[INPUT_MODE_SINGLE_END_50oHM]

signal path select:

[PATH_SEL_DIFF_ADC]

[PATH_SEL_DIFF_OFFSET_PGA_ADC]: pass through diff amplifier and Gain & Offset stage

[PATH_SEL_DIFF_OFFSET_FILTER_PGA_ADC]: pass through diff amplifie, Gain & Offset stage and low-pass filter

gain select:

[GAIN_SEL_X1]

[GAIN_SEL_X4]

[GAIN_SEL_DIV5]

[GAIN_SEL_DIV2]

diagnostic path select: ** not use for production test

[DIAG_SEL_AWG1_DIG1]

[DIAG_SEL_AWG2_DIG1]

[DIAG_SEL_AWG3_DIG1]

[DIAG_SEL_AWG1_TMU1_TMU2_RMS_DIFF]

PLL reference clock select :

[PLL_REF_SEL_10MHZ]

[PLL_REF_SEL_EXTERNAL]

Sample clock select :

[ACQU_CLK_SEL_PLL]

[ACQU_CLK_SEL_DIRECT_SAMPLING]

[ACQU_CLK_SEL_AWG1_PLL]

EXAMPLE:

DSPII_DIG_SETTING(DSPII_DIG1,0v,10khz,RLY_ON,INPUT_MODE_SINGLE_END,PATH_SEL_DIFF V50IC Test System MIX Programming Manual

V50 IC Test System MIX Programming Manual

_ADC,GAIN_SEL_X1,PLL_REF_SEL_10MHZ,ACQU_CLK_SEL_AWG1_PLL);

DESCRIPTION:

The 128K RAM Waveform Digitizer provides to the user a power measurement tool. The clock coming from the PLL may generate a sampling rate between 1 Hz and 500 kHz. Having a separate clock source for the digitizer allows the user to measure at one frequency and continue forcing data with the AWG at a higher or lower frequency.

DSPII_DIG_ACQUISITION

SYNTAX:DSPII_DIG_SRAM_READ(DIG_NO, count, start_addr, ArrayName, Compensation); ARGUMENTS:

DIG_NO : 1~8

Count : 1~128k

Start_addr : 1~128k

ArrayName : Maximum 20 characters

Compensation: the same as gain selct of DSPII_DIG_SETTING

[GAIN_SEL_X1]

[GAIN_SEL_X4]

[GAIN_SEL_DIV5]

[GAIN_SEL_DIV2]

EXAMPLE:

DSPII_DIG_SRAM_READ(DSPII_DIG1,512,0,wave_captured); DESCRIPTION:

V50IC Test System MIX Programming Manual

DSPII_DIG_SRAM_READ

SYNTAX:DSPII_DIG_SRAM_READ(DIG_NO, count, start_addr, ArrayName); ARGUMENTS:

DIG_NO : 1~8

Count : 1~128k

Start_addr : 1~128k

ArrayName : Maximum 20 characters

EXAMPLE:

DSPII_DIG_SRAM_READ(DSPII_DIG1,512,0,wave_captured); DESCRIPTION:

V50IC Test System MIX Programming Manual

DSPII_TMU_SETTING

SYNTAX:DSPII_TMU_SETTING(TMU_NO, trigger_level_a, trigger_level_b, cycle_count, [RLY_ON], [TRIGGER_SLOP_A_NEGATIVE], [TRIGGER_SLOP_B_NEGATIVE]);

ARGUMENTS:

TMU_NO : DSPII_TMU1 ~ DSPII_TMU16.

trigger_level_a : set trigger voltage for start trigger

trigger_level_b : set trigger voltage for stop trigger

cycle_count : number of cycle will be measured ( 2~65535 )

[RLY_ON] : set TMU input relay on, the default state is relay off

[TRIGGER_SLOP_A_NEGATIVE], TRIGGER_SLOP_B_NEGATIVE] : set slope of trigger start / stop, the default state is positive slope

EXAMPLE:

As shown as figure(A) :

(A).RISE TIME measurement

DSPII_TMU_SETTING(DSPII_TMU1,0.8V,3.3V,1,RLY_ON);

// ** set trigger voltage=0.8V for trigger start, trigger voltage=3.3V for trigger stop

DSPII_TMU_START(DSPII_TMU1,WAIT=5MS);

// ** start trigger and wait for 5ms

DSPII_TMU_READ(DSPII_TMU1,SOURCE_SEL_INTERVAL, UP_LIMIT=1US, DOWN_LIMIT=0.8US);

//** select TMU mode = interval mode, and read value from TMU1

(B).FALL TIME measurement

DSPII_TMU_SETTING(DSPII_TMU1,3.3V,0.8V,1,RLY_ON, TRIGGER_SLOP_A_NEGATIVE, TRIGGER_SLOP_B_NEGATIVE);

// ** set trigger voltage=3.3V for trigger start, trigger voltage=0.8V for trigger stop

DSPII_TMU_START(DSPII_TMU1,WAIT=5MS);

// ** start trigger and wait for 5ms

DSPII_TMU_READ(DSPII_TMU1,SOURCE_SEL_INTERVAL, UP_LIMIT=1US, DOWN_LIMIT=0.8US);

//** select TMU mode = interval mode, and read value from TMU1

(C). Measure Frequency

DSPII_TMU_SETTING(DSPII_TMU1,1.5V,1.5V,10);

// ** set trigger voltage=1.5V for trigger start, trigger stop is not used when using "SOURCE_SEL_FREQUENCY" mode, but user should put a reasonable value on

DSPII_TMU_START(DSPII_TMU1,WAIT=20MS);

V50IC Test System MIX Programming Manual

// ** start trigger and wait for 20ms, wait time should longger than measure time

DSPII_TMU_READ(DSPII_TMU1,SOURCE_SEL_FREQUENCY, UP_LIMIT=1100HZ, DOWN_LIMIT=900HZ);

//** select TMU mode = measure frequency mode, and read value from TMU1 DESCRIPTION:

V50IC Test System MIX Programming Manual

V50IC Test System MIX Programming Manual

SYNTAX:DSPII_TMU_START(TMU_NO,[WAIT=x]);

ARGUMENTS:

TMU_NO : DSPII_TMU1 ~ DSPII_TMU16

[WAIT] : set wait time for measurement stable, default is 10uS; ex. WAIT=5MS means wait for 5mS EXAMPLE: See “DSPII_TMU_SETTING”

DESCRIPTION: See “DSPII_TMU_SETTING”

V50IC Test System MIX Programming Manual

SYNTAX:DSPII_TMU_READ(TMU_NO, TMU mode select, [UP_LIMIT=x], [DOWN_LIMIT=x], [CLEAR_CONT]);

ARGUMENTS:

TMU_NO : DSPII_TMU1 ~ DSPII_TMU16

TMU mode select : select TMU mode

[SOURCE_SEL_INTERVAL], default

[SOURCE_SEL_MULTI_INTERVAL]

[SOURCE_SEL_FREQUENCY]

[UP_LIMIT=x] : set upper limit

[DOWN_LIMIT=x] : set lower limit

[CLEAR_CONT] : clear count of counter after read; enable when set CLEAR_CONT, default is disable EXAMPLE: See “DSPII_TMU_SETTING”

DESCRIPTION: See “DSPII_TMU_SETTING”

V50IC Test System MIX Programming Manual

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