M48Z08-100PC1;M48Z18-100PC1;中文规格书,Datasheet资料

June 2011Doc ID 2424 Rev 81/20

M48Z08M48Z18

5 V , 64 Kbit (8 Kb x 8) ZEROPOWER ? SRAM

Features

■Integrated, ultra low power SRAM and power-fail control circuit ■Unlimited WRITE cycles

■READ cycle time equals WRITE cycle time ■Automatic power-fail chip deselect and WRITE protection

WRITE protect voltages

(V PFD = power-fail deselect voltage): –M48Z08: V CC = 4.75 to 5.5 V; 4.5 V ≤ V PFD ≤ 4.75 V –M48Z18: V CC = 4.5 to 5.5 V; 4.2 V ≤ V PFD ≤ 4.5 V ■Self-contained battery in the CAPHAT? DIP package

■Pin and function compatible with JEDEC standard 8 K x 8 SRAMs

RoHS compliant

–Lead-free second level interconnect

https://www.360docs.net/doc/b31294751.html,

Contents M48Z08, M48Z18

Contents

1Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.1READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.4V CC noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 11 3Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

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M48Z08, M48Z18List of tables List of tables

Table 1.Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 2.Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 3.READ mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 4.WRITE mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 5.Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 6.Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 7.Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 8.DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 9.Power down/up AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 10.Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 11.PCDIP28 – 28-pin plastic DIP, battery CAPHAT?, package mech. data . . . . . . . . . . . . . 16 Table 12.Ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 13.Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

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List of figures M48Z08, M48Z18 List of figures

Figure 1.Logic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2.DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3.Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 4.READ mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 5.WRITE enable controlled, WRITE mode AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 6.Chip enable controlled, WRITE mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 7.Supply voltage protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 8.AC testing load circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 9.Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 10.PCDIP28 – 28-pin plastic DIP, battery CAPHAT?, package outline. . . . . . . . . . . . . . . . . 16 Figure 11.Recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4/20Doc ID 2424 Rev 8

M48Z08, M48Z18Description 1 Description

The M48Z08/18 ZEROPOWER? RAM is an 8 K x 8 non-volatile static RAM which is pin and

function compatible with the DS1225.

The monolithic chip provides a highly integrated battery-backed memory solution.

The M48Z08/18 is a non-volatile pin and function equivalent to any JEDEC standard 8 K x 8

SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the

non-volatility of PROMs without any requirement for special write timing or limitations on the

number of writes that can be performed.

The 28-pin, 600 mil DIP CAPHAT? houses the M48Z08/18 silicon with a long-life lithium

button cell in a single package.

Table 1.Signal names

A0-A12Address inputs

DQ0-DQ7Data inputs / outputs

E Chip enable

G Output enable

W WRITE enable

V CC Supply voltage

V SS Ground

NC Not connected internally

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Description M48Z08, M48Z18

6/20Doc ID 2424 Rev 8

M48Z08, M48Z18Operation modes

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2 Operation modes

The M48Z08/18 also has its own power-fail detect circuit. The control circuitry constantly

monitors the single 5 V supply for an out of tolerance condition. When V CC is out of

tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low V CC . As V CC falls below

approximately 3 V , the control circuitry connects the battery which maintains data until valid power returns.Table 2.

Operating modes

Note:

X = V IH or V IL ; V SO = Battery backup switchover voltage.

2.1 READ mode

enable) is low. The device architecture allows ripple-through access of data from eight of 65,536 locations in the static storage array. Thus, the unique address specified by the 13 address inputs defines which one of the 8,192 bytes of data is to be accessed. Valid data will be available at the data I/O pins within address access time (t AVQV ) after the last

enable access time (t ELQV ) or output enable access time (t GLQV ).

activated before t AVQV , the data lines will be driven to an indeterminate state until t AVQV . If for output data hold time (t AXQX ) but will go indeterminate until the next address access.

Mode V CC

E G W DQ0-DQ7Power Deselect 4.75 to 5.5 V

or

4.5 to

5.5 V

V IH X X High Z Standby WRITE V IL X V IL D IN Active READ V IL V IL V IH D OUT Active READ V IL V IH V IH High Z Active Deselect V SO to V PFD (min)(1)

1.See Table 10 on page 15 for details.

X X X High Z CMOS standby Deselect

≤ V SO (1)X

X

X

High Z

Battery backup mode

Operation modes M48Z08, M48Z18

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Note:Table 3.

READ mode AC characteristics

2.2 WRITE mode

EHAX from chip enable or t WHAX from WRITE Enable prior to the initiation of another READ or WRITE cycle. Data-in must be valid t DVWH prior to the end of WRITE and remain valid for t WHDX should be kept high during WRITE cycles to avoid bus contention; although, if the output bus WLQZ falls.

Symbol Parameter (1)

1.Valid for ambient operating temperature: T A = 0 to 70 °C; V CC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where noted).

M48Z08/M48Z18

Unit

Min Max

t AVAV READ cycle time

100

ns t AVQV Address valid to output valid 100ns t ELQV Chip enable low to output valid 100ns t GLQV Output enable low to output valid 50ns t ELQX (2)2.C L = 30 pF.

Chip enable low to output transition 10ns t GLQX (2)Output enable low to output transition 5

ns t EHQZ (2)Chip enable high to output Hi-Z 50ns t GHQZ (2)Output enable high to output Hi-Z 40

ns t AXQX

Address transition to output transition

5ns

M48Z08, M48Z18Operation modes

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Operation modes

M48Z08, M48Z18

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Table 4.

WRITE mode AC characteristics

2.3 Data retention mode

With valid V CC applied, the M48Z08/18 operates as a conventional BYTEWIDE? static

RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself when V CC falls within the V PFD (max), V PFD (min) window. All outputs become high impedance, and all inputs are treated as “Don't care.”

Note:

A power failure during a WRITE cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the RAM's content. At voltages below V PFD (min), the user can be assured the memory will be in a write protected state, provided the V CC fall time is not less than t F . The M48Z08/18 may respond to transient noise spikes on V CC that reach into the deselect window during the time the device is sampling V CC . Therefore, decoupling of the power supply lines is recommended.

When V CC drops below V SO , the control circuit switches power to the internal battery which preserves data. The internal button cell will maintain data in the M48Z08/18 for an accumulated period of at least 11 years when V CC is less than V SO .

As system power returns and V CC rises above V SO , the battery is disconnected, and the power supply is switched to external V CC . Write protection continues until V CC reaches V PFD (min) plus t rec (min). E should be kept high as V CC rises past V PFD (min) to prevent

inadvertent write cycles prior to system stabilization. Normal RAM operation can resume t rec after V CC exceeds V PFD (max). For more information on battery storage life refer to the application note AN1012.

Symbol Parameter (1)

1.Valid for ambient operating temperature: T A = 0 to 70 °C; V CC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where

noted).M48Z08/M48Z18

Unit

Min Max

t AVAV WRITE cycle time

100ns t AVWL Address valid to WRITE enable low 0ns t AVEL Address valid to chip enable 1 low 0ns t WLWH WRITE enable pulse width

80ns t ELEH Chip enable low to chip enable 1 high 80ns t WHAX WRITE enable high to address transition 10ns t EHAX Chip enable high to address transition 10ns t DVWH Input valid to WRITE enable high 50ns t DVEH Input valid to chip enable 1 high 30ns t WHDX WRITE enable high to input transition 5ns t EHDX Chip enable high to input transition 5

ns t WLQZ (2)(3)2.C L = 30 pF.

3.If E goes low simultaneously with W going low, the outputs remain in the high impedance state.

WRITE enable low to output Hi-Z 50ns t AVWH Address valid to WRITE enable high 80ns t AVEH

Address valid to chip enable high

80ns t WHQX (2)(3)WRITE enable high to output transition

10

ns

分销商库存信息:

STM

M48Z08-100PC1M48Z18-100PC1

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