BK4800_10_Datasheet V0.4

BK4800_10_Datasheet V0.4
BK4800_10_Datasheet V0.4

Preliminary Specification for VB3 (ES4)

400 MHz Analog Two Way Radios IC

Approvals

Name Date Signature

Beken Corporation

Suite 303-304, No. 10, 198 Zhangheng Rd, Shanghai 201204, China

PHONE: (86)21 5080 7801

FAX: (86)21 6160 9679

This document contains information that may be proprietary to, and/or secrets of, Beken Corporation. The contents of this document should not be disclosed outside the companies without specific written permission.

Disclaimer: Descriptions of specific implementations are for illustrative purpose only, actual hardware implementation may differ. ? 2008 Beken Corporation Proprietary and Confidential Page 1 of 56

Revision History

Version Date Author(s) Description

0.2 2009/11/09 Beken Initial draft for BK48 V12 based on “BK4800-

01_Datasheet V0.4.doc” at 2009/07/08 and

“BK4810_Datasheet V0.1.doc” at 2009/08/27 and

“BK4800 Design Specification.doc” at 2009/09/04 0.3 2009/12/01 Beken Modify VDDPA18 REG7[13:10] from D to F; Add a

note that AFC should be disable in FSK AIR receiver

mode

0.4 2010/2/26 Beken Update pin definition and package pin order

Update register initial setting

Add mute hysteresis; audio PA gain

? 2008 Beken Corporation Proprietary and Confidential Page 2 of 56

Content

1 General Description 4

2 Key Features 4

3 Applications 5

4 Chip Block Diagram 5

5 Pin Information 6

6 Functional Description 8 6.1 RF Functions 8 6.2 TX Baseband 9

6.2.1 Audio 9

6.2.2 VOX and TOT 11

6.2.3 In-band Signaling 11

6.2.3.1 DTMF 12

6.2.3.2 FSK 12

6.2.3.3 SELCALL 13

6.2.4 Sub-audible Signaling 13 6.3 RX Baseband 14

6.3.1 Audio 14

6.3.2 In-band Signaling 15

6.3.2.1 DTMF 15

6.3.2.2 FSK 16

6.3.2.3 SELCALL 16

6.3.3 Sub-audible Signaling 17 6.4 Operate Mode Control 17

6.5 Temperature Sensor 17

7 MCU Interface 18 7.1 Interface Timing 18

7.2 Interface Register Definition 18

8 Electrical Specification 52

9 Application Schematic 54

10 Package 55

11 Order Information 56 ? 2008 Beken Corporation Proprietary and Confidential Page 3 of 56

1 General Description

BK4800/10 is a half duplex TDD FM transceiver operating in the 400 MHz license free band for worldwide personal radio service. The transceiver integrated high performance PLL, ADC, DAC, and advanced digital signal processing capability on a single chip. The digital low-IF image rejection architecture enables it to work with a very simple MCU as a two way radio communication system. On-chip flexible and precise continuous and discrete tone generator and detector enable a secure link and digital signaling.

BK4800/10 on-chip FSK data modem supports F2D and F1W emission to be used in both FRS and DPMR band for text message and GPS information exchange besides speech communication.

BK4800 and BK4810 have no difference in current stage.

2 Key Features

?World wide band: 400 ~ 470 MHz

?12.5/25 kHz channel spacing

? 2.55/3 kHz audio filter

?On chip 5 dBm RF PA

?Integrated ADC for external temperature sensor circuit

? 2.4 V to 4.5 V power supply

?CTCSS tone receiver with up to parallel eight frequency detector

?23/24 bit programmable DCS code

?Standard DTMF and programmable in-band dual tone

?SELCALL and programmable in-band single tone

? 1.2/2.4 kbps FSK data modem with either F2D or F1W modulation type

?Frequency inversion scrambler and enhanced analog speech encryption

?Voice activated switch (VOX) and time-out timer

?RF Signal strength measurement and signal quality measurement

?TX Audio signal strength indication and RX audio signal strength indication

?Adaptive noise suppression with fast soft mute

?Integrated 250 mW audio PA at 2.8 power supply

?EARON can be used as audio input to be amplified by internal audio PA

?3-wires or 2-wiers interface with MCU with maximum 8 Mbps clock rate

?QFN 7x7 48-Pin package, naked die or COB (for development)

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3 Applications

Personal radio service

Toys

Baby monitor

4 Chip Block Diagram

Figure 1 BK4800/10 Chip Block Diagram

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5 Pin Information

VDDRF LNAIN LNASOUR

VDDPA18PADOUTN

VSSPA VDDPA CPOUT2

NC M I C I P

M I C I N

C R E F

X T A L P

X T A L N

R R E F

T M P I N N

T M P I N P

V D D T X A

U D

V S S T X A U D

VSSXTAL

CDVDD EXTLNA EXTPA SCLK SEN SDIO IRQ DV2V5GBATD VBATD CEB V D D S P K S P K O P S P K O N V S S S P K

E A R O N

E A R O P

V D D A U D

V S S A U D

V S S I F A D C R E F N

A D C R E F P

V D D I F

VBAT

G B A T

A V 2V 5

Figure 2 BK4800/10 Pin Assignment

Table 1 BK4800/10 Pin Definition of V14

Pin # PinName cPAD # cPAD Name Power of domain Function

2

VDDRF

1

VDDRF

2.4V to

3.6V

VDD to RF regulator supply

3 LNAin 2 LNAin 1.8V LNA input port

4 LNAsour 3 LNAsour 1.8V LNA input port

(Connect to GND through inductor) 5

VSSRF

4

VSSRF

GND

Ground to RF

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5 VSSRF2 GND Connect to the same Pin for VSSRF

6 VDDPA18 6 VDDPA18 1.8V PAD regulator output (programmable)

7 PADOUTN

7

PAOUTN

1.8V

TX RF output

PADOUT 8 PAOUT NC 8 VSSPA 9 VSSPA GND Ground to PAD

9

VDDPA

10

VDDPA

2.4V to

3.6V

VDD to PAD regulator supply 10 CPout2 11 CPout2 1.8V

Ramping output voltage

11 Cpout 12 Cpout 1.8V NC 12 VBAT 13 VBAT 2.4V to 4.5V

Battery supply to analog section 13

GBAT

14

GBAT

GND

Ground to analog section

14 AV2V5 15 AV2V5 2.5V 2.5V analog regulator output

15 MICIP 16 MICIP VDDTXAUD Microphone input 16 MICIN 17 MICIN VDDTXAUD Microphone input 17

CREF

18

CREF

1.2V

Central bias decoupling cap

18 XTALP 19 XTALP 1.8V Crystal oscillator port 19

XTALN

20

XTALN

1.8V

Crystal oscillator port

20 RREF 21 RREF VBAT

Central bias internal node decoupling

Connected to GND via a decoupling Cap CKtest 22 CKtest 1.8V

Mixed-signal test output

NC

RSSI 23 RSSI 1.8V

RX IF RSSI output

NC 21 TMPINN 24 TMPINN 1.8V ADC input for measuring external DC 22 TMPINP 25 TMPINP 1.8V

ADC input for measuring external DC 23

VDDTXAUD

26

VDDTXAUD

2.4V to

3.6 V

VDD (2.5V) to TX Audio signal chain 24 VSSTXAUD 27 VSSTXAUD GND Ground to analog TX audio section 25

VSSXTAL

28

VSSXTAL

GND Ground to crystal oscillator

26 CDVDD 29 CDVDD 1.8V Digital 1.8V regulator output

Connected to GND via a decoupling Cap GPIO4 30 GPIO4 1.8V Test Pin

NC (reg117<9:0>=10'h155) GPIO3 31 GPIO3 1.8V Test Pin

NC (reg117<9:0>=10'h155) GPIO2 32 GPIO2 1.8V Test Pin

NC (reg117<9:0>=10'h155) GPIO1 33 GPIO1 1.8V Test Pin

NC (reg117<9:0>=10'h155) GPIO0 34 GPIO0 1.8V Test Pin

NC (reg117<9:0>=10'h155) 27 EXTLNA 35 EXTLNA VBAT Switch control to an external LNA 28

EXTPA

36

EXTPA

VBAT

Switch control to an external PA

29 SCLK 37 SCLK 1.8V SPI Clock 30 SEN 38 SEN 1.8V SPI Enable 31 SDIO 39 SDIO 1.8V SPI Data 32 IRQ 40 IRQ 1.8V Interrupt Signal to MCU 33 DV2V5

41 DV2V5 2.5V 2.5V Digital Regulator Output

42

GBATD2

GND

Connect to the same Pin for GBAT

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34 GBATD 43 GBATD GND Ground to Digital Section 35

VBATD

44

VBATD

2.4V to 4.5V

Battery Supply to Digital Section

36 CEB 45 CEB DIG High=power down; Low=active 37

VDDSPK

46

VDDSPK

2.4V to 4.2V Battery Supply to Speaker Driver 38 SPKOP 47 SPKOP VDDSPK Speaker Driver Output 39 SPKON 48 SPKON VDDSPK Speaker Driver Output 40

VSSSPK

49

VSSSPK

GND

Ground to Speaker Driver

41 EARON 50 EARON VDDAUD Earpiece Output 42 EAROP 51 EAROP VDDAUD Earpiece Output 43 VDDAUD 52 VDDAUD

2.4V to

3.6V

VDD Supply to RX Audio

tQDo 53 tQDo 1.8V

IF ADC Test Output

NC

tIDo 54 tIDo 1.8V

IF ADC Test Output

NC 44 VSSAUD 55 VSSAUD GND Ground to RX Audio 45 VSSIF 56 VSSIF GND Ground to RX IF 46 ADCREFN 57 ADCREFN 1.8V IF ADC Reference (N) 47 ADCREFP

58 ADCREFP

1.8V

IF ADC Reference (P)

tVIp 59 tVIp 1.8V IF Analog test output tVQp 60 tVQp 1.8V IF Analog test output 48 VDDIF 61 VDDIF 1.8V IF Regulator output (1.8 V)

1

CVRF

62

CVRF

1.8V

RF LNA+Mixer Regulator output (1.8 V)

6 Functional Description

6.1 RF Functions

BK4800/10 integrates a complete FM transceiver. The receiver includes all functions from the antenna input to the data/audio output. The transmitter includes all functions from the data/audio input to the antenna output, and it has a programmable ramping table. The ramping time can be varied from 0.16 ms to 20 ms (REG42, REG43). The typical transmit power is 5 dBm (50 Ohm load).

BK4800/10 supports programmable frequency from 400 MHz to 470 MHz with less than 10 Hz resolution (REG112, REG113, and REG114). The first channel frequency setting is calculated as follows.

)67.21/26^2*3125_/26^2*(e e REF F f round N ?=

In formula above, the F is the desired first channel frequency and F_REF is the reference clock, which is 21.7 MHz normally or is the crystal frequency if the DPLL is bypassed. The MSB 16 bits of N is REG113 and LSB 16 bits of N is REG114.

The TX and RX channel frequency calculation is the same: F_CHAN = F + CH_NUM * CH_SPACE, where channel number CH_NUM is set by REG112 and channel spacing CH_SPACE is set by REG01.

Deviation of audio band signal and sub-audible band signal can be programmed independently (REG40).

BK4800/10 receiver can detect signal strength and give out 7 bit RSSI (REG68) with 1 dB resolution. The signal quality SNR (REG68) can also be detected and a value of 6 bit width (with value from 0 to 63 dB) can be read through the MCU interface. The internal RF AFC (REG69, REG70) enables receiver to lock to the transmitter frequency, but AFC should be disabled for FSK AIR receiver. The internal RF AGC (REG108, REG109) enables receiver to automatically control its front end gain to the best status). When receive signal is too weak and SNR is too low (REG67), the audio path can be automatically muted with both either soft mute or hard mute (REG73).

The BK4800/10 has an external PA output power control pin VDDPA18, whose voltage can be programmed with REG7 [13:10].

6.2TX Baseband

6.2.1Audio

TX audio path has the following blocks:

Digital AGC to automatically adjust microphone gain (REG44, REG45) before ADC ADC gain block to compensate analog to digital conversion loss (REG17)

Two stage high pass filter HPF1 and HPF2 to remove DC in audio signal (REG17) Volume control with 1 dB step from -25 dB to 6 dB (REG18)

Optional pre-emphasis filter, 0 dB at 1 kHz and +6 dB per octave (REG18)

Optional audio scrambling based on either frequency inversion with programmable inversion frequency, or strong audio encryption with programmable code word

z Programmable frequency inversion point (REG20)

z Programmable encryption code word (REG120)

z Combined encryption mode (REG121) which should enable both audio encryption and CDCSS

Optional 300 Hz high pass filter to avoid interference to sub-audible signal, which has 30 dB attenuation for frequency below 250 Hz with respect to signal at 1 kHz (REG18)

Optional low pass filter with 2.55 kHz corner for 12.5 kHz channel spacing and 3 kHz corner for 25 kHz channel spacing (REG18)

Limiter to avoid unwanted out-of-band emission (REG18)

Flexible block execution order (REG18)

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Figure 3 TX Audio Block Diagram

10

10

10

1010

Pre Emphasis Frequency Response

Frequency (Hz)

A m p l i t d u e (d

B )

Figure 4 Pre-emphasis Filter Frequency Response

10

10

10

10

10

10

10

300 Hz High Pass Filter Frequency Response

Frequency (Hz)

A m p l i t d u e (d

B )

Figure 5 300 Hz High Pass Filter Frequency Response

The microphone gain can be control through REG44 and REG45.

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Gain1Gain2

Figure 6 Microphone Gain before ADC

(

10log *201Riin

Riex Rf

Gain +=.

The resistance of Riin is 2.15 k ohm.

The resistance of Rf is 100 k ohm (REG44 [5] = 1) and 16 ohm (REG44 [5] = 1). User can adjust the external Riex resistor to adjust the Gain1.

The Gain 2 is linear controlled by REG44 [4:0], with 0 is 6.5 dB and 31 is 22 dB.

When AGC is enabled, the Gain1 and Gain 2 control word REG44 [5:0] is automatically controlled by internal AGC algorithm.

6.2.2 VOX and TOT

Voice activated switch (VOX) detects the background noise level (REG22) and

microphone input signal level (REG21), when the ratio between the signal level and the background noise level is greater than a programmable threshold (REG22) and the signal level is greater than an absolutely threshold (REG21), the VOX will output 1 and the VOX interrupt bit will be set (REG116).

The time constant of the signal level detector and the background noise level detector are programmable (REG22).

VOX works only when receive signal strength (REG68) is lower than a programmable threshold (REG67) for a programmable duration (REG22).

In TX mode, time-out timer (TOT) detects the VOX output, if it is 0 (no active

microphone input signal) for a programmable duration (REG23), the TOT interrupt bit will be set (REG116).

6.2.3 In-band Signaling

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There are three types of in-band signaling: DTMF, SELCALL, and FSK (and FSK_AIR). Together with audio signal, they are total of four kinds of in-band signaling, of which only one can be sent at a time (REG40). The deviation of in-band signaling is programmable (REG40).

6.2.3.1 DTMF

DTMF is a dual tone signaling, it has programmable high band and low band frequency. The high band frequency can be programmable from 1209 Hz to 1633 Hz (REG25). The low band frequency can be programmable from 697 Hz to 941 Hz (REG24). The twist can be programmable from 0 to 15 dB with 1 dB resolution (REG26)). The suggested DTMF tone table is given below.

Table 2 Standard DTMF Table

DTMF Symbol High Frequency (Hz)

1209 1336

1447 1633

Low

Frequency (Hz) 697

1 2 3 A 770

4 5 6 B 852

7 8 9 C 941 E

0 F D

6.2.3.2 FSK

FSK is a high data rate signaling, which supports 1200 bps data mode at 12.5 kHz

channel spacing and 2400 bps data mode at 25 kHz channel spacing. The frame structure of the data package is given below.

Figure 7 Frame Structure of Data Mode

User can write head field including Addr/Type/Size/CRCA and the corresponding

payload (REG28, REG29, REG30), and BK4800/10 will automatically calculate the CRC and packetize the data. Optional scrambling can be added to Addr and subsequent bytes, and the scrambling seed is programmable (REG32).

Data receiver will automatically finish synchronization and data extraction that Addr/Type/Size/CRCA and Payload can be read out through MCU interface.

The final over the air data package type can be setting with Type byte.

Type 0: Only head, no payload

Type 1: Head with payload

Type 2: Head with FEC encoded payload

Type 3: Head with FEC and interleaved encoded payload

Type 4: Free format that no automatic CRC insertion, CRCA is a user writable byte

The payload write is through an 8 words (1 word = 2 bytes) FIFO, if the word number in FIFO is shorter than a threshold that a write operation requires, it will give an interrupt to MCU that MCU must refill the FIFO (REG31).

Note: if use type 3, the number of payload is restricted. The allowed payload number is either odd number less than 8 or even number greater than 9. Payload number 8 and 9 is not allowed for type 3.

The FSK packet can be transmitted either directly through FM modulation (FSK AIR) for DPMR band or with a MSK modulated sub-carrier (FSK modem) then to FM modulation for FRS band.

6.2.3.3SELCALL

SELCALL is a single tone signaling, the frequency can be programmable from 400 Hz to 3000 Hz (REG34). To get high sensitivity the suggested tone frequency (EIA frequency group) is given below.

Table 3 EIA single tone frequency setting

Tone Number 0 1 2 3 4 5 6 7

Tone Frequency (Hz) 600 7418821023116413051446 1587

Tone Number 8 9 A B C D E F

Tone Frequency (Hz) 1728 18692151243520102295495 No Tone

6.2.4Sub-audible Signaling

Sub-audible signaling includes both CTCSS and CDCSS. For CTCSS, the frequency is programmable with 18 bit resolution, and it can be set to have a 0/120/180 degree phase shift. For CDCSS, it supports both standard CDCSS code with programmable 9 bit raw code and user programmable 23/24 bits CDCSS code, and the transmitted CDCSS code can be inversed.

Table 4 Reference CTCSS Frequency

Standard CTCSS Tone

? 2008 Beken Corporation Proprietary and Confidential Page 13 of 56

Freq. (Hz) Freq. (Hz) Freq. (Hz) Freq. (Hz)Freq. (Hz)Freq. (Hz)Freq. (Hz)

67.0 85.4 103.5127.3 156.7 192.8 241.8

71.9 88.5 107.2 131.8 162.2 203.5 250.3

74.4 91.5 110.9 136.5 167.9 210.7

77.0 94.8 114.8 141.3 173.8 218.1

79.7 97.4 118.8 146.2 179.9 225.7

82.5 100.0 123.0 151.4 186.2 233.6

Non-Standard CTCSS Tone

Freq. (Hz) Freq. (Hz) Freq. (Hz) Freq. (Hz)Freq. (Hz)Freq. (Hz)Freq. (Hz)

62.5 69.3183.5 196.6 206.5

64.7 159.8189.9 199.5 229.1

Table 5 Reference CDCSS Raw 9 bit Octal Word

023 025 026 031 032 036 043 047

051 053 054 065 071 072 073 074

114 115 116 122 125 131 132 134

143 145 152 155 156 162 165 172

174 205 212 223 225 226 243 244

245 246 251 252 255 261 263 265

266 271 274 306 311 315 325 331

332 343 346 351 356 364 365 371

411 412 413 423 431 432 445 446

452 454 455 462 464 465 466 503

506 516 523 526 532 546 565 606

612 624 627 631 632 654 662 664

703 712 723 731 732 734 743 754

6.3RX Baseband

The RX baseband output is the FM demodulator output, whose amplitude can be scaled (REG66), and subsequent filter coefficient is selected according to the in-band signal type (REG66) and sub-audible signal type (REG66).

6.3.1Audio

Audio path has blocks below:

Optional three high pass filter, where HPF1 is a simple filter for DC blocking, HPF2 is same as 300 Hz high pass filter in TX audio path, and HPF3 is used to compensate de-emphasis filter (REG72)

Optional de-emphasis filter, 0 dB at 1 kHz and -6 dB per octave (REG72)

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Optional audio de-scrambling based on either frequency inversion with

programmable inversion frequency, or strong audio de-encryption with programmable code word

z Programmable frequency inversion point (REG74) z Programmable de-encryption code word (REG120)

z Combined de-encryption mode (REG121) which enable both audio de-encryption

and CDCSS decoder (REG94)

Optional low pass filter with 2.55 kHz corner for 12.5 kHz channel spacing and 3.1

kHz corner for 25 kHz channel spacing (REG72)

45 dB volume control range with 3 dB per step (REG73)

Hard mute or soft mute control based on receive signal quality (REG73)

Flexible block execution order (REG72)

Figure 8 TX Audio Block Diagram

10

10

10

1010

5

Frequency (Hz)

A m p l i t d u e (d

B )

De-emphasis Frequency Response

Figure 9 De-emphasis Filter Frequency Response

The RX signal strength before volume control module can be read out through REG74.

6.3.2 In-band Signaling

6.3.2.1 DTMF

DTMF decoder can detect up to 16 DTMF symbols simultaneously (REG78). High band tone frequency and low band tone frequency of each symbol can be programmed

individually (REG77). When the decoder finds a symbol match, it will set corresponding bit and the found symbol address (REG78), and an interrupt will be issued.

User can trade off detection sensitivity with response time by selection different match condition and their detection margin (REG75, REG76).

There are two symbol match conditions; the first (match condition 1) is the tone frequency variance less than a programmable margin DTMF_MARGIN2, and the second (match condition 2) is the tone frequency stay inside a deviation (DTMF_MARGIN1) from reference frequency for a programmable duration (DTMF_MARGIN3). User can enable either one of them or both of them for DTMF symbol match. SELCALL and CTCSS have the same match algorithm.

6.3.2.2FSK

In FSK AIR mode, the slicer output of FM demodulator will be FSK symbol. In FSK mode, the FM demodulator output is taken as a sub-carrier, and will be demodulated with a FSK demodulator.

FSK receiver will search the sync word to establish synchronization with FSK transmitter. When it is synchronized and CRCA check is passed, a FSK head received interrupt (REG116) will be issued and it will continue to receive the payload. The payload data

will be written to an 8 words FIFO, and when the data word number in FIFO is greater than a threshold that the FIFO needs to read out, it will issue an interrupt (REG116) and MCU should read out all data bytes in FIFO immediately (REG82, REG83). After all payload of one packet is received, the CRCB check result will be set (REG83) and a receive- finished interrupt will be issued to MCU that MCU should check this bit to know whether the read out payload is valid or invalid that should be discarded.

Note: With free format type (type 4), the “ FSK head received interrupt” will be given out immediately when it found the sync word , thus, this interrupt is earlier than that in other mode.

6.3.2.3SELCALL

SELCALL decoder can detect up to 16 SELCALL symbols simultaneously (REG87). Frequency of each symbol can be programmed individually (REG86). When the decoder find a symbol match, it will set corresponding bit and the found symbol address (REG87), and an interrupt will be issued.

User can trade off detection sensitivity with response time by selection different match condition and their detection margin (REG84, REG85).

There is an optional high pass filter to filter out signal below 400 Hz (REG87), and user can bypass this filter to receive SELCALL symbol with frequency below 400 Hz.

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6.3.3Sub-audible Signaling

CTCSS decoder can detect up to 8 CTCSS symbols simultaneously (REG92). Frequency of each symbol can be programmed individually (REG91). When the decoder find a symbol match, it will set corresponding bit and the found symbol address (REG92), and an interrupt will be issued.

User can trade off CTCSS detection sensitivity with response time by selection different match condition and their detection margin (REG89, REG90).

CTCSS decoder has an optional high pass filter to filter out DC signal (REG92), which can be used to get better RF frequency offset and low frequency noise immunity. CDCSS decoder uses the same setting as CDCSS encoder, and has also an optional DC block filter (REG94).

6.4Operate Mode Control

BK4800/10 has three operation modes: transmit mode, receive mode and power down mode. Pull pin CEB high will power down the whole chip. REG112 [14] is used to set the chip to either transmit mode or receive mode. The mode switch is always controlled by MCU. No automatic mode switch is inside BK4800/10. Besides power down mode, the BK4800/10 can be set to an idle mode, which is same as power down mode except all register setting is kept.

BK4800/10 has a voice activity sensor, if there is an active voice at microphone input when no receive signal, BK480x will give a VOX interrupt to MCU when VOX mode is enabled, and MCU should switch BK4800/10 to transmit mode.

BK4800/10 also has a programmable time-out timer that if no voice activity for a programmable duration from 0.5 to 60 second at transmit mode, BK4800/10 will give a TOT interrupt to MCU when TOT is enabled, and MCU should switch BK4800/10 to either receive mode or power down mode.

6.5Temperature Sensor

BK4800/10 has an ADC for external voltage input of temperature sensor; its output can be read from REG0. MCU can adjust the first channel frequency according to REG0 to keep RF frequency offset between RX and TX in a small range such as 2.5 PPM.

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7 MCU Interface

The MCU interface mainly consists of an IRQ interrupt and a register access interface, either a 3-wires SPI interface or a 2-wires interface. User could select either of them by

setting the state of SEN pin on the falling edge of pin CEB (Pin CEB from 1 to 0) or on the transition from no power (VBAT=0) to power ready. It will use 3-wires interface for

SEN=0 or 2-wires interface for SEN=1.

7.1 Interface Timing

Figure 10 3-wires Interface Timing

Figure 11 2-wiers Interface Timing

BK4800/10 always latch data at the SCLK rising edge and output its data at SCLK falling edge. For 2-wiers host reading, the host must give an ACK to BK4800/10 after each byte access, and should give a NACK to BK4800/10 after last byte read out.

7.2 Interface Register Definition

Table 6 Interface Register Definition

Address (DEC )

R/W Default Value

Sub-module Description

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Page 19 of 56

00 R 0x0000 Common 15:8 Device ID

0x04

7:0 Temperature

01 W/R 0x0000 Common 0x0000

Channel spacing 15 Channel spacing: 0: 12.5 kHz,

1: 25 kHz

14

FSK_AIR data rate 0:1.2kbps 1:2.4kbps

13:8 Reserved 7:0 Chip ID

0xB3 for BK4800VB3

02 – 15

RF/Analog

Please use initialize value below

02 W 0x0000 0x1DE4 03 W 0x0000 0xFD59 04 W 0x0000 0x0521 05 W 0x0000 0x3708 06 W 0x0000 0x02BF

10:9

Audio PA Gain 0: 1 1: 2 2: 4 3: 8

07 W 0x0000 0xBD03

6

Power down RX AGC 0: Power up 1: Power down

4

Power down Clock 0: Power up 1: Power down

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3

Power down RF PLL (also power down temperature sensor ADC and RX AGC) 0: Power up 1: Power down

2

Power down RX chain (except PLL and RX AGC and EARO/Class-D) 0: Power up 1: Power down

1

Power down TX chain (except MIC and PLL) 0: Power up 1: Power down

Power down temperature sensor ADC 0: Power up 1: Power down

08 W 0x0000 0x4233

3

Audio earpiece power down 0: Power up 1: Power down

2

Class-D PA speaker source 0: From internal RX speech 1: From external EARP/EARN

Class-D PA power down 0: Power up 1: Power down

09 W 0x0000 0x0638

2:0 Temperature sensor gain

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