一款基于65nm CMOS工艺的高效率50GHz压控振荡器及其电感耦合效应的研究

Vol.34,No.7Journal of

Semiconductors July 2013

A 65nm CMOS high efficiency 50GHz VCO with regard to the coupling effect of inductors

Ye Yu(叶禹)1;2; and Tian Tong(田彤)3

1Key

Laboratory of Terahertz Solid-State Technology,Shanghai Institute of Micro-system and Information Technology,Chinese Academy of Sciences,Shanghai 200050,China

2University of Chinese Academy of Sciences,Beijing 100049,China

3Internet of Things System Technology Laboratory,Shanghai Institute of Micro-system and Information Technology,Chinese Academy of Sciences,Shanghai 200050,China

Abstract:A 50GHz cross-coupled voltage controlled oscillator (VCO)considering the coupling effect of induc-tors based on a 65nm standard complementary metal oxide semiconductor (CMOS)technology is reported.A pair of inductors has been fabricated,measured and analyzed to characterize the coupling effects of adjacent inductors.The results are then implemented to accurately evaluate the VCO’s LC tank.By optimizing the tank voltage swing and the buffer’s operation region,the VCO achieves a maximum efficiency of 11.4%by generating an average output power of 2.5dBm while only consuming 19.7mW (including buffers).The VCO exhibits a phase noise of 87dBc/Hz at 1MHz offset,leading to a figure of merit (FoM)of –167.5dB/Hz and a tuning range of 3.8%(from 48.98to 50.88GHz).

Key words:CMOS;coupling effects;inductors;LC tank;VCO DOI:10.1088/1674-4926/34/7/075001EEACC:1350H;2570D

1.Introduction

V oltage controlled oscillators (VCOs)are key building

blocks in millimeter-wave (mm-wave)integrated circuits due to the increasing demand for wide band and high data rate communication systems.Therefore,great efforts have been made to enhance the performance of mm-wave VCOs ?1 3 .For VCOs employing an LC tank as a resonator,such as the Col-pitts or cross-coupled VCO,the oscillation frequency is de-termined by the values of the tank inductors and capacitors.Hence,it is important to study the parasitic effects which af-fect the total equivalent values of the tank.Recently,as im-plemented in high frequencies,LC tank VCOs face increased challenges of coupling effects due to miniaturization.Tank in-ductors need to be placed very close to each other in layout.Although special technologies have been applied to de-couple those inductors on a process level,such as guard-rings and deep n-well technology,there are still strong coupling effects be-tween the adjacent inductors introducing parameter drift.Pre-vious works on coupling inductors ?4;5 were not intended for application in VCO design.Another key issue in VCOs is to improve power efficiency while exhibiting high output power.To achieve high efficiency,the CMOS VCO is significant in lowering the whole power dissipation in mm-wave systems.Recently,CMOS VCOs operating at around 50GHz or higher regularly have low output power and low efficiency ?6;7 .

In this work,an extraction of the coupling effects in a VCO’s tank inductor has been adopted to obtain the accuracy value of the inductor.A high quality factor (Q -factor)metal–oxide–metal (MOM)capacitor has been implemented to gain high power efficiency.Section 2extracts the coupling effects.

The proposed VCO topology and measured results are illus-trated in Sections 3and 4.Conclusions are drawn in Section 5.

2.Coupling effects of inductors

Different from Ref.[4],adjacent cascaded inductors are focused upon in this work,corresponding to the implementa-tion in a VCO’s LC tank.Figures 1(a)and 1(b)illustrate the micro-photograph of the element and cascaded fabricated spi-ral inductor.Except for the number of cascaded inductor,the sizes of the inductors are identical in this work.The inner dia-meter of each inductor is 11 m,the width of inductor is 3 m,and the gap between metal lines is 3 m,respectively.The edge distance between two adjacent inductors is set to 40 m ?4 .

The effective inductance (L eff /and the effective Q -factor (Q eff /are extracted from the measured S -parameters where de-embedding technology has been implemented ?5 .As shown in Fig.2(a),two de-embedded S -parameters of the elemental in-

Fig.1.Microphotographs of the element inductor and the cascaded inductor.(a)Element inductor.(b)Cascaded inductor.

*Project supported by the Special Fund on IOT Technology Research from China Government (No.YORSKB1001).?Corresponding author.Email:yye@https://www.360docs.net/doc/b812643677.html,

Received 26November 2012,revised manuscript received 27January 2013?2013Chinese Institute of Electronics

Fig.2.Coupling effects measurement for inductors with single-ended configuration.(a)With element inductor S -parameter in series.(b) With cascaded inductor S-parameter.

Fig.3.Simulated and measured L eff and Q eff with/without coupling effects.

ductor are connected in series to represent the cascaded induc-tor without coupling effects.The cascaded inductor consider-ing coupling characteristic is depicted in Fig.2(b).Both are single-ended driven and the characteristics are compared with simulated results based on HFSS.The simulated and measured L eff and Q eff with or without coupling effects are shown in Fig.3.

3.The proposed VCO topology

The proposed VCO is indicated in Fig.4,in which the cross coupled pair is utilized to compensate the loss in res-onators,such as parasitic resistance.The core consists of a neg-ative channel metal oxide semiconductor(NMOS)cross cou-pled pair(M1and M2),which provides negative resistance, and an LC tank(C1,C v1,C2,C v2,L1,L2/.A positive chan-nel metal oxide semiconductor(PMOS)tail transistor M3is employed as the current source to reduce the1=f noise?7 . 3.1.LC tank

The schematic of the tank inductor’s structure is shown in Fig.5(a)and the simulation results are indicated in Fig.5(b), with and without coupling effects.Based on the results ob-served in Section2,the edge distance is set to40 m,trading off between the inductor sizes and coupling effects.Simulated results show an8.6%reduction in L eff which means an actual 115pH for half the tank regarding the mutual inductance.

The half equivalent circuit of the proposed core VCO is featured in Fig.6,where the coupled pair M1and M2is mod-eled as a negative conductance G m1and a shunt capacitance C pm1representing parasitic capacitance caused by transistors. The lossy element is represented as G p,whereas C pBUF is buffer input capacitance.There is a trade-off between output power and frequency tuning range(FTR).To meet the start-up con-dition,the channel width of M1/M2only needs to be set as 8 m.Under the identical conditions such as the same LC tank and the same direct current(DC)supply,the enlargement of the channel width could increase the input current of the core VCO,which can indeed be exploited to achieve a higher out-put power and thus increase efficiency.?8 Hence,to gain a high output swing and efficiency the designed channel width needs to be extended to12 m.However,simultaneously,the in-creased parasite capacitance of the larger transistor will add to the LC tank in parallel.While the other passive LC tank stays the same,the added bypass parasite capacitance reduces the FTR.Another trade-off exists between phase noise and FTR. To improve the phase noise performance,the Q-factor of the LC tank needs to be enhanced?9 .As in Ref.[7],the Q-factor of the tank is more limited by the varactor but not the inductor in mm-wave regime.To compensate the low Q-factor caused by the accumulation MOS(AMOS)varactor,a high Q-factor MOM capacitor has been connected in parallel with the AMOS varactor to form the varactor C v1and C v2,as shown in Fig.7. The varactor C v1and C v2are connected with MOM capacitor C1and C2,respectively.As depicted in Fig.7,such a config-uration of capacitors in the tank could enhance the Q-factor compared with the only adoption of low Q-factor AMOS var-actors.However,by adding fixed MOM capacitors,such a configuration could reduce the FTR of the VCO at the same time.

3.2.Buffer

In this work,a two-stage buffer amplifier with transistors in common-source(CS)configuration is employed?2 to fur-ther boost the output power,in which the first stage transis-tor size is tapered to minimize the effect of the buffers on the LC tank.The circuit schematic of the output buffer is shown in Fig.8.The buffer’s supply is cut down to0.7V to achieve high efficiency whereas keeping good linearity of the output swing.

In order to further maximize the output swing and the ef-ficiency of the VCO,the bias of the second stage transistor has been adjusted to hold the transistor working in the class-AB region.As shown in Fig.8,the gate bias of M6is set as 0.7V,while M7is biased at0.55V.The first stage transis-tor is chosen to be small for good isolation between the sec-ond stage transistor and the core VCO,while keeping the sig-nal’s linearity.The second stage transistor is chosen to be large for high power output,while it operates in class-AB to cut off the power consumption thus to enhance power efficiency.Be-cause the core VCO output and the tank share the same ter-minals,the attached buffer amplifier has an influence on the tank impedance.Hence,the buffer needs to be carefully de-signed with the impedance matching.In this work,the on-chip inductors,with the inductance of165pH and220pH re-spectively,have been implemented for their ease of matching and low insertion loss.With respect to the operation in mm-wave,such implementations could enhance the VCO’s effi-ciency.

Fig.4.The topology of the50GHz cross-coupled VCO with buffers.

Fig.5.The structure and simulated results of the tank inductor.(a) Simulated model of the tank inductor.(b)Simulated L eff and

Q eff of the tank inductor with/without coupling effects.

4.

Measurement results

By utilizing a65nm CMOS1P8M standard process from

Fig.6.The equivalent half circuit of the LC tank.

Fig.7.Configuration of capacitors in the LC tank. UMC,a50GHz cross-coupled VCO with differential outputs is implemented in the core circuit.Buffers are used to isolate the core circuit from subsequent circuits and to achieve high output power with high efficiency.Figure9shows the micro-graph of the fabricated circuit,in which a symmetrical archi-tecture and layout are implemented to ensure the fully differen-tial operation of M1and M2.The total chip area,including the DC and radio frequency(RF)pads,is0.6 0.45mm2,where the active area only occupies0.45 0.3mm2.The VCO is characterized on-wafer,using an Agilent N9030A PXA for fre-quency,power and phase noise measurements.The spectrum

Fig.8.The circuit topology of the output buffer (one side).

Fig.9.Microphotograph of the proposed VCO.

Fig.10.Simulated and measured frequency and output power tuning curve.(a)Oscillation frequency.(b)Output power.(One-side output)

analyzer is connected to one of the VCO’s outputs,while the other one is terminated by a 50 load.Corrections for cable loss and single-ended measurement are applied.?8 At the max-imum linearity bias point the VCO core draws 12mA from 1V supply and the buffers draw 11mA from 0.7V supply,with the total 19.7mW power consumption.

As illustrated in Fig.10(a),the measured oscillation fre-quency is from 48.98to 50.88GHz,which corresponds to a FTR of 3.8%,with the controlled voltage,V TUNE ,from 0to 1.8V

.The simulation results with considering the adjacent in-

Fig.11.Measured phase noise of the proposed VCO at 50.88GHz.

ductors’coupling effect show better matching with measure-ments than the results derived from the simulation without considering the adjacent inductors’coupling effect.The nearly 10%differences in the simulated oscillation frequencies with-out regarding the coupling effect are because of the inaccu-rate effective inductance of the tank inductor.The figure il-lustrates that to get an accurate oscillation frequency,the cou-pling effect of the adjacent inductor should be considered in the LC tank VCO’s design.As featured in Fig.10(b),the out-put power simulation results with and without considering the adjacent inductors’coupling are almost the same.It is because the parasitic resistor depends on the lossy substrate,the metal conductance and size,but has little relationship with the cou-pling effect.Figure 10(b)shows that the one-side output power is around 0:5dBm over the whole tuning voltage interval in which the maximum one-side output power of 0.5dBm is achieved at 49.71GHz,whereas the simulated one-side out-put power is around 0.5dBm.The combined output power is more than 2.5dBm over the whole operation frequencies,while achieving a maximum 3.5dBm output power.This VCO also achieves a maximum efficiency of 11.4%and an average ef-ficiency of 9.1%over the entire FTR,respectively.In this pa-per,larger transistors in the tank are adopted for the potentially high headroom of voltage swing and thus linearity,high Q -factor on-chip inductors have been implemented for low loss matching and buffers working in Class-AB region have been employed.The high output power and efficiency performance could be ascribed to such changes.As far the currently avail-able literature by the authors is concerned,this is the highest output power when adopting the CMOS process around V-band or higher.

Measured phase noise at 50.88GHz is depicted in Fig.11,where the minimum value of 87dBc/Hz and 100dBc/Hz are achieved at 1MHz and 10MHz offset,respectively.Ta-ble 1shows the performance in comparison with some other published VCOs.A modified FoM including output power ?8 demonstrates that the presented VCO exhibits good perfor-mance.

5.Conclusion

In this paper,the coupling effects between cascaded induc-tors have been studied and then implemented in an LC cross-coupled CMOS VCO design.The VCO exhibits an average

https://www.360docs.net/doc/b812643677.html,pared performance of VCOS.

Reference Cao?2 Jimenez?6 Kim?7 Kraemer?8 Chiu?10 Li?11 This work Technology(CMOS)130nm65nm130nm65nm180nm90nm65nm

f0(GHz)595647596961.750 Phase noise

@1MHz(dBc/Hz)

89 99:4 95:4 90:3 76:2 90 87

FTR(%) 5.817 3.35 5.47.5 4.81 3.8

P dc(mW)9.824.6 3.8616.527.52 1.219.7

P rf(dBm) 10 9:3 15 0:9 18:5 19 3.5*

P rf=P dc(%) 1.00.470.08 4.90.07 1.311.4* FoM(dB/Hz) 173:1 185:1 182:9 168:2 158 186 167:5 FoMP**(dB/Hz) 163:1 175:8 167:9 167:3 139:5 167 167

*Combined the two differential ports.

**FoMP D FoM–10log10(P rf/1mW)

2.5dBm output power and average9.1%efficiency over the whole FTR while only consumes19.7mW,whereas achieves a minimum phase noise of–87dBc/Hz at1MHz offset and a FTR of

3.8%(48.98to50.88GHz).The maximum out-put power of3.5dBm and maximum efficiency of11.4%are achieved for the VCO.

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