DN2540N3-G中文资料

Features

High input impedance Low input capacitance Fast switching speeds Low on resistance

Free from secondary breakdown Low input and output leakage

Applications

Normally-on switches Solid state relays Converters Linear ampli? ers

Constant current sources Power supply circuits Telecom

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General Description

The Supertex DN2540 is a low threshold depletion mode (normally-on) transistor utilizing an advanced vertical DM OS structure and Supertex’s well-proven silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coef? cient inherent in M OS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally-induced secondary breakdown.

Supertex’s vertical DM OS FETs are ideally suited to a wide range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired.

N-Channel Depletion-Mode

Vertical DMOS FETs

-G indicates package is RoHS compliant (‘Green’)(1) Same as SOT-89.

Absolute Maximum Ratings

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground.*Distance of 1.6mm from case for 10 seconds.

Pin Con? gurations

3-Lead TO-243AA (N8)

3-Lead TO-220 (N5)

3-Lead TO-92 (N3)

GATE SOURCE

DRAIN

DRAIN

GATE

SOURCE

DRAIN

GATE

SOURCE DRAIN

DRAIN

DN2540

Thermal Characteristics

Notes:

(1) I D (continuous) is limited by max rated T j .

(2) Mounted on FR5 board, 25mm x 25mm x 1.57mm.

Product Marking

3-Lead TO-243AA (N8)

3-Lead TO-220 (N5)

3-Lead TO-92 (N3)

Electrical Characteristics (T

@ 25O C unless otherwise speci? ed)

L = Lot Number YY = Year Sealed WW = Week Sealed

= “Green” Packaging

YY = Year Sealed WW = Week Sealed

= “Green” Packaging

W = Code for week sealed

DN2540

Notes:

1.All D.C. parameters 100% tested at 25O C unless otherwise stated. (Pulse test: 300μs pulse, 2% duty cycle.)

2.All A.C. parameters sample tested.

OUTPUT INPUT

OUTPUT

0V

V DD

0V

-10V

Switching Waveforms and Test Circuit

DN2540

Typical Performance Curves

Output Characteristics

0.5

0.4

0.3

0.2

0.1

Saturation Characteristics

V GS = 1.0V 0.5V 0V

-0.5V

-1.0V

1

1000

100

10

1

0.1

0.01

0.001

0.001

10

0.01

0.1

1

0.5

0.4

0.3

0.2

0.1

0I D )

s e r e p m a ( G S F )

s n e m e i s ( V DS (volts)I D )

s e r e p m a ( t p (seconds)

DN2540

Typical Performance Curves (cont.)

BV DSS Variation with Temperature

V B S S D d

e z i l a m r o N 1.1

1.05

1.0

0.950.9

V DS (Volts)I D )

s e r e p m a ( 0.40

0.32

0.240.16

0.08

0)

s d a r a f o c i P ( C 200

150

100

50

00

10

20

30

40

On-Resistance vs. Drain Current

Q C (Nanocoulombs)

0.4

0.8

1.2

1.6

2.0

DN2540

3-Lead TO-92 Package Outline (N3)

Drawings not to scale.

DN2540 3-Lead TO-220 (Power Package) Package Outline (N5)

JEDEC Registration TO-220, Variation AB, Issue K, April 2002.

Drawings not to scale.

DN2540

(The package drawing(s) in this data sheet may not re? ect the most current speci? cations. For the latest package outline information go to https://www.360docs.net/doc/cd8795101.html,/packaging.html .)

3-Lead TO-243AA (SOT-89) Package Outline (N8)

JEDEC Registration TO-243, Variation AA, Issue C, July 1986.Drawings not to scale .

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