DM74LS112AMX中文资料

? 2000 Fairchild Semiconductor Corporation DS006382

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August 1986Revised March 2000

DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs

DM74LS112A

Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs

General Description

This device contains two independent negative-edge-trig-gered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flop on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the transition time of the falling edge of the clock pulse. Data on the J and K inputs may be changed while the clock is HIGH or LOW without affecting the outputs as long as the setup and hold times are not violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs.

Ordering Code:

Devices also available in T ape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram Function Table

H = HIGH Logic Level L = LOW Logic Level

X = Either LOW or HIGH Logic Level ↓ = Negative Going Edge of Pulse

Q 0 = The output logic level before the indicated input conditions were established.

Toggle = Each output changes to the complement of its previous level on each falling edge of the clock pulse.Note 1: This configuration is nonstable; that is, it will not persist when preset and/or clear inputs return to their inactive (HIGH) level.

Order Number Package Number

Package Description

DM74KS112AM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74LS112AN

N16E

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Inputs

Outputs

PR CLR CLK J K Q Q L H X X X H L H L X X X L H L L X X X H (Note 1)

H (Note 1)

H H ↓L L Q 0Q 0H H ↓H L H L H H ↓L H L

H H ↓H H Toggle

Q 0Q 0

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D M 74L S 112A

Absolute Maximum Ratings (Note 2)

Note 2: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings.The “Recommended Operating Conditions” table will define the conditions for actual device operation.

Recommended Operating Conditions

Note 3: C L = 15 pF, R L = 2 k ?, T A = 25°C and V CC = 5V.

Note 4: The symbol (↓) indicates the falling edge of the clock pulse is used for reference.Note 5: C L = 50 pF, R L = 2 k ?, T A = 25°C and V CC = 5V.

Supply Voltage 7V Input Voltage

Operating Free Air Temperature Range 0°C to +70°C Storage Temperature Range

?65°C to +150°C

Symbol Parameter

Min Nom Max Units V CC Supply Voltage

4.755

5.25

V V IH HIGH Level Input Voltage 2

V V IL LOW Level Input Voltage 0.8V I OH HIGH Level Output Current ?0.4mA I OL LOW Level Output Current 8mA f CLK Clock Frequency (Note 3)030MHz f CLK Clock Frequency (Note 5)025

MHz

t W

Pulse Width Clock HIGH 20(Note 3)

Preset LOW 25ns

Clear LOW 25t W

Pulse Width Clock HIGH 25(Note 5)

Preset LOW 30ns Clear LOW

30t SU Setup Time (Note 3)(Note 4)20↓ns t SU Setup Time (Note 4)(Note 5)25↓ns t H Hold Time (Note 3)(Note 4)0↓ns t H Hold Time (Note 4)(Note 5)5↓ns T A

Free Air Operating Temperature

°C

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DM74LS112A

Electrical Characteristics

over recommended operating free air temperature range (unless otherwise noted)Note 6: All typicals are at V CC = 5V, T A = 25°C.

Note 7: Not more than one output should be shorted at a time, and the duration should not exceed one second. For devices, with feedback from the outputs,

where shorting the outputs to ground may cause the outputs to change logic state an equivalent test may be performed where V O = 2.125V with the minimum and maximum limits reduced by one half from their stated values. This is very useful when using automatic test equipment.

Note 8: With all outputs OPEN, I CC is measured with the Q and Q outputs HIGH in turn. At the time of measurement the clock is grounded.

Switching Characteristics

at V CC = 5V and T A = 25°C

Symbol Parameter

Conditions

Min

Typ Max Units (Note 6)

V I Input Clamp Voltage V CC = Min, I I = ?18 mA ?1.5

V V OH HIGH Level V CC = Min, I OH = Max 2.7

3.4V

Output Voltage V IL = Max, V IH = Min V OL

LOW Level V CC = Min, I OL = Max

0.350.5Output Voltage

V IL = Max, V IH = Min V

I OL = 4 mA, V CC = Min 0.25

0.4I I

Input Current @ Max V CC = Max, V I = 7V

J, K 0.1Input Voltage

Clear 0.3mA

Preset 0.3Clock

0.4I IH

HIGH Level Input Current

V CC = Max, V I = 2.7V

J, K 20Clear 60μA Preset 60Clock

80I IL

LOW Level Input Current

V CC = Max, V I = 0.4V

J, K ?0.4Clear ?0.8mA Preset ?0.8Clock

?0.8I OS Short Circuit Output Current V CC = Max (Note 7)?20

?100mA I CC

Supply Current

V CC = Max (Note 8)

mA From (Input)

R L = 2 k ?

Symbol Parameter

To (Output)

C L = 15 pF C L = 50 pF Units

Min Max

f MAX Maximum Clock Frequency 30

MHz t PLH Propagation Delay Time Preset to Q 2024ns LOW-to-HIGH Level Output t PHL Propagation Delay Time Preset to Q 2028ns HIGH-to-LOW Level Output t PLH Propagation Delay Time Clear to Q 2024ns LOW-to-HIGH Level Output t PHL Propagation Delay Time Clear to Q 2028ns HIGH-to-LOW Level Output t PLH Propagation Delay Time Clock to Q or Q 2024ns LOW-to-HIGH Level Output t PHL

Propagation Delay Time Clock to Q or Q 2028ns HIGH-to-LOW Level Output

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D M 74L S 112A

Physical Dimensions

inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

Package Number M16A

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N16E

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1.Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to the user.

2. A critical component in any component of a life support

device or system whose failure to perform can be rea-

sonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

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https://www.360docs.net/doc/c014644518.html, DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs