EDA 电子设计自动化

107页
mywork.vhd程序:
library ieee;
use ieee.std_logic_1164.all;
package mywork is
function max (a:std_logic_vector;
b:std_logic_vector)
return std_logic_vector;
type week is (sun,mon,tue,wed,thu,fri,sat);
end mywork;
package booy mywork is
function max(a:std_logic_vector;
b:std_logic_vector(3 downto 0))return std_logic_vector is
variable temp:std_logic_vector(3 downto 0);
begin
if(a>b)then
temp0:=a;
else
temp:=b;
end if;
return temp;
end max;
end mywork;


ex5.vhd程序:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library work;
use work.mywork.all;

entity ex5 is
port(d0,d1:in std_logic_vector(3 downto 0);
clk:in std_logic;
q:out std_logic_vector(2 downto 0);
count:out std_logic_vector(2 downto 0));
end ex5;
architecture a of ex5 is
begin
q<=max(d0,d1);
process(clk)
variable count0:week;
begin
if clk'event and clk='1'then
case count0 is
when sun=>count0:=mon;
when mon=>count0:=tue;
when tue=>count0:=wed;
when wed=>count0:=thu;
when thu=>count0:=fri;
when fri=>count0:=sat;
when sat=>count0:=sun;
end case;
end if;
case count0 is
when sun=>count<="111";
when mon=>count<="001";
when tue=>count<="010";
when wed=>count<="011";
when thu=>count<="100";
when fri=>count<="101";
when sat=>count<="110";
end case;
end process;
end a;

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