CNT10

CNT10设计

源程序：

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity cnt10 is

port(CLK,RST,EN:in std_logic;

CQ:out std_logic_vector(3 downto 0);

COUT:out std_logic);

end cnt10;

architecture behav of cnt10 is

begin

process(CLK,RST,EN)

variable CQI:std_logic_vector(3 downto 0);

begin

if RST='1' then CQI:=(others =>'0');

elsif CLK' event and CLK='1' then

if en ='1' then

if CQI< 9 then CQI:=CQI+1;

else CQI:=(others=>'0');

end if;

end if;

end if;

if CQI=9 then COUT<='1';

else COUT<='0';

end if ;

CQ<=CQI;

end process;

end behav;

波形