PDM41024SA10SOI中文资料

PDM41024

Absolute Maximum Ratings (1)

Symbol Rating Com’l.Ind.Unit

V TERM T erminal Voltage with Respect to V SS–0.5 to +7.0–0.5 to +7.0V

T BIAS T emperature Under Bias–55 to +125–65 to +135°C

T STG Storage T emperature–55 to +125–65 to +150°C

P T Power Dissipation 1.0 1.0W

I OUT DC Output Current5050mA

T j Maximum Junction T emperature (2)125145°C

NOTE:1.Stresses greater than those listed under ABSOLUTE MAXIMUM RA TINGS may cause permanent damage to the device. This is a stress rating only and functional operation of

the device at these or any other conditions above those indicated in the operational

sections of this speci?cation is not implied. Exposure to absolute maximum rating con-

ditions for extended periods may affect reliability.

2. Appropriate thermal calculations should be performed in all cases and speci?cally for

those where the chosen package has a large thermal resistance (e.g., TSOP). The cal-

culation should be of the form: T j = T a + P * θja where T a is the ambient temperature, P

is average operating power and θja the thermal resistance of the package. For this

product, use the following θja values:

SOJ: 72o C/W

TSOP: 95o C/W

PDM41024

PDM41024

Capacitance (1) (T A = +25 ° C, f = 1.0 MHz)

NOTE:1.This parameter is determined by device characterization but is not production tested.

AC Test Conditions

Symbol Parameter Max.Unit C IN Input Capacitance 8pF C OUT

Output Capacitance

8

pF

Input pulse levels V SS

to 3.0V

Input rise and fall times 3 ns Input timing reference levels 1.5V Output reference levels 1.5V

Output load

See Figures 1 and 2

Figure 1. Output Load Equivalent

Figure 2. Output Load Equivalent (for t LZCE , t HZCE , t LZWE , t HZWE , t LZOE ,

t HZOE

)

PDM41024

12

345

6

78

9101112

Read Cycle No. 1(4, 5)

Read Cycle No. 2(2, 4, 6)

AC Electrical Characteristics

SHADED AREA = PRELIMINARY DA TA

Notes referenced are after Data Retention T able.

PDM41024 Write Cycle No. 1 (Write Enable Controlled)

Write Cycle No. 2 (Write Enable Controlled)

PDM41024

1

23

456

789101112

Write Cycle No. 3 (Chip Enable Controlled)

AC Electrical Characteristics

SHADED AREA = PRELIMINARY DAT A

Notes referenced are after Data Retention Table

PDM41024

Low V CC Data Retention Waveform

Data Retention Electrical Characteristics (LA Version Only) for JEDEC Version

NOTES: (For three previous Electrical Characteristics tables)

1.The parameter is tested with CL = 5 pF as shown in Figure

2. Transition is measured ±200 mV from steady state voltage.2.At any given temperature and voltage condition, t HZCE is less than t LZCE .

3.This parameter is sampled.

4.WE is high for a READ cycle.

5.The device is continuously selected. All the Chip Enables are held in their active state.

6.The address is valid prior to or coincident with the latest occurring Chip Enable.

7.Vcc = 5V ± 5%.

Ordering Information

Symbol Parameter

Test Conditions

Min.Typ.Max.Unit V DR V CC for Retention Data 2——V I CCDR

Data Retention Current

CE1 ≥ V CC – 0.2V or CE2 ≤ V SS + 0.2V V IN ≥ V CC – 0.2V or ≤ 0.2V

V CC = 2V ——500μA V CC = 3V

750

μA

t CDR Chip Deselect to Data Retention Time 0——ns t R (3)

Operation Recovery Time

t RC

ns

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