OPA659中文资料

FEATURES

DESCRIPTION

APPLICATIONS

TRANSIMPEDANCE GAIN vs FREQUENCY (C = 22pF)

D 130120

110100908070605040T r a n s i m p e d a n c e G a i n (d B )

W 100k

1M 10M

100M

Frequency (Hz)

Photo Diode

OPA659

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Wideband,Unity-Gain Stable,

JFET-Input

OPERATIONAL AMPLIFIER

?HIGH BANDWIDTH:650MHz (G =+1V/V)The OPA659combines a very wideband,unity-gain stable,voltage-feedback operational amplifier with a ?HIGH SLEW RATE:2550V/μs (4V Step)JFET-input stage to offer an ultra-high dynamic range ?EXCELLENT THD:–78dBc at 10MHz

amplifier for high impedance buffering in data ?LOW INPUT VOLTAGE NOISE:8.9nV/√Hz acquisition applications such as oscilloscope ?FAST OVERDRIVE RECOVERY:8ns

front-end amplifiers and machine vision applications such as photodiode transimpedance amplifiers used ?FAST SETTLING TIME (1%4V Step):8ns in wafer inspection.

?LOW INPUT OFFSET VOLTAGE:±1mV The wide 650MHz unity-gain bandwidth is ?LOW INPUT BIAS CURRENT:±10pA complemented by a very high 2550V/μs slew rate.?

HIGH OUTPUT CURRENT:70mA

The high input impedance and low bias current provided by the JFET input are supported by the low 8.9nV/√input voltage noise to achieve a very low ?HIGH-IMPEDANCE DATA ACQUISITION INPUT integrated noise in wideband photodiode AMPLIFIER

transimpedance applications.

?HIGH-IMPEDANCE OSCILLOSCOPE INPUT Broad transimpedance bandwidths are possible with AMPLIFIER

the high 350MHz gain bandwidth product of this ?WIDEBAND PHOTODIODE TRANSIMPEDANCE device.

AMPLIFIER

Where lower speed with lower quiescent current is ?

WAFER SCANNING EQUIPMENT

required,consider the OPA656.Where unity-gain stability is not required,OPA657.

OPERATIONAL AMPLIFIER

PRODUCTS

Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.Copyright ?2008,Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas Instruments standard warranty.Production processing does not necessarily include testing of all parameters.

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ABSOLUTE MAXIMUM RATINGS

1 2 3 48

+V S

Output

NC Inverting Input Noninverting Input

-V S

+V S

Inverting Input Output

-V S

Noninverting Input

OPA659

SBOS342–https://www.360docs.net/doc/f18715276.html, This integrated circuit can be damaged by ESD.Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions.Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure.Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION(1)

SPECIFIED

PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT PACKAGE-LEAD DESIGNATOR RANGE MARKING NUMBER MEDIA,QUANTITY

OPA659IDBVT Tape and reel,250 OPA659SOT23-5DBV–40°C to+85°C BZX

OPA659IDBVR Tape and reel,3000

OPA659IDRBT Tape and reel,250 OPA659VSON-8DRB–40°C to+85°C OBFI

OPA659IDRBR Tape and reel,3000

(1)For the most current package and ordering information see the Package Option Addendum at the end of this document,or see the TI

web site at https://www.360docs.net/doc/f18715276.html,.

Over operating free-air temperature range(unless otherwise noted).

OPA653UNIT Power Supply Voltage V S+to V S–±6.5V

Input Voltage±V S V

Input Current100mA

Output Current100mA

Continuous Power Dissipation See Thermal Characteristics

Operating Free Air Temperature Range,T A–40to+85°C

Storage Temperature Range–65to+150°C

Lead Temperature(soldering,10s)+260°C

Maximum Junction Temperature,T J+150°C

Maximum Junction Temperature,T J(continuous operation for long term reliability)+125°C Human Body Model(HBM)4000V

ESD

Charge Device Model(CDM)1000V Rating:

Machine Model200V

DRB PACKAGE DRV PACKAGE

VSON-8SOT23-5

(TOP VIEW)(TOP VIEW)

Note:NC:Not connected.

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ELECTRICAL CHARACTERISTICS:V S=±6V OPA659

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At R F=0?,G=+1V/V,and R L=100?,T A=+25°C,unless otherwise noted.

OPA659

TEST PARAMETER CONDITIONS MIN TYP MAX UNIT LEVEL(1) AC PERFORMANCE

Small-Signal Bandwidth V O=200mV PP,G=+1V/V650MHz C

V O=200mV PP,G=+2V/V335MHz C

V O=200mV PP,G=+5V/V75MHz C

V O=200mV PP,G=+10V/V35MHz C Gain Bandwidth Product G>+10V/V350MHz C

Bandwidth for0.1dB Flatness G=+2V/V,V O=2V PP55MHz C

Large-Signal Bandwidth V O=2V PP,G=+1V/V575MHz B

Slew Rate V O=4V Step,G=+1V/V2550V/μs B

Rise and Fall Time V O=4V Step,G=+1V/V 1.3ns C

Settling Time to1%V O=4V Step,G=+1V/V8ns C

Pulse Response Overshoot V O=4V Step,G=+1V/V12%C

Harmonic Distortion V O=2V PP,G=+1V/V,f=10MHz

2nd harmonic–79dBc C

3rd harmonic–100dBc C

V O=2V PP Envelope(each tone1V PP),

Intermodulation Distortion

G=+2V/V,f1=10MHz,f2=11MHz

2nd intermodulation–72dBc C

3rd intermodulation–96dBc C Input Voltage Noise f>100kHz8.9nV/√Hz C

Input Current Noise f<10MHz 1.8fA/√Hz C

DC PERFORMANCE

Open-Loop Voltage Gain(A OL)T A=+25°C,V CM=0V,R L=100?5258dB A

T A=–40°C to+85°C,V CM=0V,R L=100?4955dB B Input Offset Voltage T A=+25°C,V CM=0V±1±5mV A

T A=–40°C to+85°C,V CM=0V±1.5±7.6mV B Average Offset Voltage Drift T A=–40°C to+85°C,V CM=0V±10±40μV/°C B Input Bias Current T A=+25°C,V CM=0V±10±50pA A

T A=0°C to+70°C,V CM=0V±240±1200pA B

T A=–40°C to+85°C,V CM=0V±640±3200pA B

T A=0°C to+70°C,V CM=0V±5±26pA/°C B Average input bias current drift

T A=–40°C to+85°C,V CM=0V±7±34pA/°C B Input Offset Current T A=+25°C,V CM=0V±5±25pA A

T A=0°C to+70°C,V CM=0V±120±600pA B

T A=–40°C to+85°C,V CM=0V±320±1600pA B INPUT

Common-Mode Input Range T A=+25°C±3±3.5V A

T A=–40°C to+85°C±2.87±3.37V B Common-Mode Rejection Ratio T A=+25°C,V CM=±0.5V6870dB A

T A=–40°C to+85°C,V CM=±0.5V6466dB B Input Impedance

Differential?pF C

10121

Common-mode?pF C

1012 2.5

(1)Test levels:(A)100%tested at+25°C.Over temperature limits set by characterization and simulation.(B)Limits set by characterization

and simulation.(C)Typical value only for information.

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OPA659

SBOS342–https://www.360docs.net/doc/f18715276.html, ELECTRICAL CHARACTERISTICS:V S=±6V(continued)

At R F=0?,G=+1V/V,and R L=100?,T A=+25°C,unless otherwise noted.

OPA659

TEST PARAMETER CONDITIONS MIN TYP MAX UNIT LEVEL(1)

OUTPUT

Output Voltage Swing T A=+25°C,No Load±4.6±4.8V A

T A=+25°C,R L=100?±3.8±4.0V A

T A=–40°C to+85°C,No Load±4.45±4.65V B

T A=–40°C to+85°C,R L=100?±3.65±3.85V B

Output Current,Sourcing,Sinking T A=+25°C±60±70mA A

T A=–40°C to+85°C±56±65mA B

Closed-Loop Output Impedance G=+1V/V,f=100kHz0.04?C

POWER SUPPLY

Operating Voltage±3.5±6±6.5V B

Quiescent Current T A=+25°C30.53233.5mA A

T A=–40°C to+85°C28.335.7mA B

Power-Supply Rejection Ratio(PSRR)T A=25°C,V S=±5.5V to±6.5V5862dB A

T A=–40°C to85°C,V S=±5.5V to±6.5V5660dB A

THERMAL CHARACTERISTICS

Specified Operating Range

–40+85°C C DRB and DRV Packages

Thermal Resistance,θJA Junction-to-ambient

DRB VSON-855°C/W C

DRV SOT23-5105°C/W C

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TYPICAL CHARACTERISTICS OPA659

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Table of Graphs

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TYPICAL CHARACTERISTICS

024********

--------N o r m a l i z e d S i g n a l G a i n (d B )

100k

10M 100M 1G

Frequency (Hz)

024********

--------N o r m a l i z e d S i g n a l G a i n (d B )

100k

10M 100M 1G

Frequency (Hz)

024********

--------N o r m a l i z e d S i g n a l G a i n (d B )

100k

10M 100M 1G

Frequency (Hz)

024********

--------N o r m a l i z e d S i g n a l G a i n (d B )

100k

10M 100M

Frequency (Hz)

024********

--------N o r m a l i z e d S i g n a l G a i n (d B )

100k 1M

10M 100M

Frequency (Hz)

024********

--------N o r m a l i z e d S i g n a l G a i n (d B )

100k

10M 100M

Frequency (Hz)

OPA659

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At V S =±6V,R F =0?,G =+1V/V,and R L =100?,unless otherwise noted.

NONINVERTING SMALL-SIGNAL FREQUENCY RESPONSE

NONINVERTING LARGE-SIGNAL FREQUENCY RESPONSE

(V O =200mV PP )

(V O =2V PP )

Figure 1.

Figure 2.

NONINVERTING LARGE-SIGNAL FREQUENCY RESPONSE

INVERTING SMALL-SIGNAL FREQUENCY RESPONSE

(V O =6V PP )

(V O =200mV PP )

Figure 3.

Figure 4.

INVERTING LARGE-SIGNAL FREQUENCY RESPONSE

(V O =2V PP )

(V O =6V PP )

Figure 5.Figure 6.

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0.30.20.100.10.20.3

---V /V (V )

I N O U T 0

Time (ns)

V OUT V IN

1.51.00.500.51.01.5

---V /V (V )

I N O U T 0

Time (ns)

V OUT V IN

3.52.51.5

0.50.51.52.53.5

----V /V (V )

I N O U T 0

Time (ns)

V OUT V IN

0.30.20.100.10.20.3

---V /V (V )

I N O U T 0

2030

4050

Time (ns)

V OUT V IN

1.51.00.500.51.01.5

---V /V (V )

I N O U T 0

Time (ns)

V OUT V IN

3.52.51.5

0.50.51.52.53.5

----V /V (V )

I N O U T 0

Time (ns)

V OUT V IN

OPA659

TYPICAL CHARACTERISTICS (continued)

At V S =±6V,R F =0?,G =+1V/V,and R L =100?,unless otherwise noted.

NONINVERTING TRANSIENT RESPONSE (0.5V STEP)

NONINVERTING TRANSIENT RESPONSE (2V STEP)

Figure 7.

Figure 8.

NONINVERTING TRANSIENT RESPONSE (5V STEP)

INVERTING TRANSIENT RESPONSE (0.5V STEP)

Figure 9.

Figure 10.

INVERTING TRANSIENT RESPONSE (2V STEP)

INVERTING TRANSIENT RESPONSE (5V STEP)

Figure 11.Figure 12.

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-5060708090100110

------H a r m o n i c D i s t o r t i o n (d B c )

100

Frequency (MHz)

-50556065707580859095100

----------H a r m o n i c D i s t o r t i o n (d B c )

Noninverting Gain (V/V)

-50556065707580859095100

----------H a r m o n i c D i s t o r t i o n (d B c )

100200300400500600700800900

R ()

W LOAD

-50556065707580859095100

----------H a r m o n i c D i s t o r t i o n (d B c )

Inverting Gain (V/V)

-5060708090100110

------H a r m o n i c D i s t o r t i o n (d B c

)

V (V )

OUT PP 6

--------7075

80859095100105110

-H a r m o n i c D i s t o r t i o n (d B

c )

4.0

4.5

5.0

5.5

6.0

±Supply Voltage (V)

OPA659

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TYPICAL CHARACTERISTICS (continued)

At V S =±6V,R F =0?,G =+1V/V,and R L =100?,unless otherwise noted.

HARMONIC DISTORTION vs NONINVERTING GAIN

HARMONIC DISTORTION vs FREQUENCY

AT 10MHz

Figure 13.

Figure 14.

HARMONIC DISTORTION vs INVERTING GAIN

HARMONIC DISTORTION vs LOAD RESISTANCE

AT 10MHz

Figure 15.

Figure 16.

HARMONIC DISTORTION HARMONIC DISTORTION vs OUTPUT VOLTAGE

vs ±SUPPLY VOLTAGE

Figure 17.Figure 18.

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321

0123

---642

246

---V (V )

I N V (V)OUT 0

6080

120

100

Time (ns)

-40

5060708090100

------I n t e r m o d u l a t i o n D i s t o r t i o n (d B c )

100

150

Frequency (MHz)

321

0123

---642

---V (V )

I N V (V)OUT 0

6080

120

100

Time (ns)

1000

100

1I n p u t -R e f e r r e d V o l t a g e N o i s e (n V /)I n p u t -R e f e r r e d C u r r e n t N o i s e (f A /H z H z )

??10

100

10k

100k

10M

Frequency (Hz)

8070

6050403020100

C M R R , P S R

R (d B )

100k

10M 100M Frequency (Hz)

100

R ()

W I S O 10100

1000

Capacitive Load (pF)

OPA659

TYPICAL CHARACTERISTICS (continued)

At V S =±6V,R F =0?,G =+1V/V,and R L =100?,unless otherwise noted.

TWO-TONE,SECOND-AND THIRD-ORDER IMD

vs FREQUENCY

OVERDRIVE RECOVERY (GAIN =+2V/V)

Figure 19.

Figure 20.

INPUT-REFERRED VOLTAGE AND CURRENT NOISE

OVERDRIVE RECOVERY (GAIN =–2V/V)

DENSITY

Figure 21.

Figure 22.

COMMON-MODE REJECTION RATIO AND POWER-SUPPLY REJECTION RATIO

RECOMMENDED R ISO

vs FREQUENCY

vs CAPACITIVE LOAD (R LOAD =1k ?)

Figure 23.Figure 24.

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10k

100k

10M

100M

Frequency (Hz)

6050

4030201001020

--O p e n -L o o p G a i n (d B )

Open-Loop Phase ()

°0

135

180

----

101520

-----G a i n (d B )

100k

10M 100M

Frequency (Hz)

100

0.1

0.01

C l o s e d L o o p

O u t p u t I m p e d a n c e ()

W 100k

1M 10M 100M 1G

Frequency (Hz)

130120

1101009080706050

40T r a n s i m p e d a n c e G a i n (d B )

W 100k

10M

100M

Frequency (Hz)

130120

110100908070605040T r a n s i m p e d a n c e G a i n (d B )

W 100k

1M 10M

100M

Frequency (Hz)

130120

1101009080706050

40T r a n s i m p e d a n c e G a i n (d B )

W 100k

10M 100M

Frequency (Hz)

OPA659

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TYPICAL CHARACTERISTICS (continued)

At V S =±6V,R F =0?,G =+1V/V,and R L =100?,unless otherwise noted.

FREQUENCY RESPONSE

vs CAPACITIVE LOAD (R LOAD =1k ?)

OPEN-LOOP GAIN AND PHASE

Figure 25.

Figure 26.

CLOSED-LOOP OUTPUT IMPEDANCE

TRANSIMPEDANCE GAIN vs FREQUENCY

vs FREQUENCY (C D =10pF)

Figure 27.

Figure 28.

TRANSIMPEDANCE GAIN TRANSIMPEDANCE GAIN vs FREQUENCY (C D =22pF)

vs FREQUENCY (C D =47pF)

Figure 29.Figure 30.

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54321012345

-----±V (V )

O U T 101001000

R ()

W LOAD

130120

1101009080706050

40T r a n s i m p e d a n c e G a i n (d B )

W 100k

10M

100M

Frequency (Hz)

3000

2000

1000

0S l e w R a t e (V /s )

m 0

V / V (V)

OUT STEP OPA659

TYPICAL CHARACTERISTICS (continued)

At V S =±6V,R F =0?,G =+1V/V,and R L =100?,unless otherwise noted.

TRANSIMPEDANCE GAIN MAXIMUM/MINIMUM ±V OUT

vs FREQUENCY (C D =100pF)

vs R LOAD

Figure 31.

Figure 32.

SLEW RATE vs V OUT STEP

Figure 33.

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APPLICATION INFORMATION

Wideband,Noninverting Operation

OPA659

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Voltage-feedback op amps can use a wide range of resistor values to set the gain.To retain a controlled The OPA659is a very broadband,unity-gain stable,

frequency response for the noninverting voltage voltage-feedback amplifier with a high impedance amplifier of Figure 35,the parallel combination of R F JFET-input stage.Its very high gain bandwidth ||R G be less than 200?.In the product (GBP)of 350MHz can be used to either noninverting configuration,the parallel combination of deliver high signal bandwidths for low-gain buffers,or R F ||R G forms a pole with the parasitic input and to deliver broadband,low-noise,transimpedance board layout capacitance at the inverting input of the bandwidth to photodiode-detector applications.The OPA659.For best performance,this pole should be OPA659is designed to to provide very low distortion at a frequency greater than the closed-loop and accurate pulse response with low overshoot and bandwidth for the OPA659.For this reason,a direct ringing.To achieve the full performance of the short from the output to the inverting input is OPA659,careful attention to printed circuit board recommended for the unity-gain follower application.(PCB)layout and component selection are required,Table 1lists several recommended resistor values for as discussed in the remaining sections of this data gains with a 50?input/output match.

sheet.

Figure 34shows the noninverting gain of +1circuit;Figure 35shows the more general circuit used for gains.These circuits are used as the basis for most of the noninverting gain Typical Characteristics graphs.Most of the signal sources with 50?driving impedance,and with measurement equipment presenting a 50?load impedance.In Figure 34,the shunt resistor R T at V IN should be to match the source impedance of the test generator and cable,while the series output resistor,R OUT ,at V OUT should also be set to 50?to provide matching impedance for the measurement equipment load and cable.Generally,data sheet voltage swing Figure 35.General Noninverting Test Circuit specifications are measured at the output pin,V OUT ,in Figure 34and Figure 35.

Table 1.Resistor Values for Noninverting Gains

with 50?Input/Output Match

NONINVERTING

GAIN

R F R G R T R OUT +10Open 49.949.9+224924949.949.9+524961.949.949.9+10

249

27.4

49.9

Figure 34.Noninverting Gain of +1Test Circuit

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Wideband,Inverting Gain Operation

Wideband,High-Sensitivity,Transimpedance

OPA659

Figure 36shows the noninverting input tied directly to a bias current-cancelling resistor to The circuit of Figure 36shows the inverting gain test ground is included here to nullify the dc errors caused circuit used of the inverting Typical by input bias current effects.For a JFET input op Characteristics graphs.As with the amp such as the OPA659,the input bias currents are of the curves were characterized so low that dc errors caused by input bias currents using signal sources with 50?driving impedance,are negligible.Thus,no bias current-cancelling and with measurement equipment that presents a resistor is recommended at the noninverting input.

50?load impedance.In Figure 36,the shunt resistor R T at V IN should be set combination of the shunt resistor and R G equals 50?to match the Design

source impedance of the test generator and cable,while the series output resistor R OUT at V OUT should The high GBP and low input voltage and current also be set to 50?to provide matching impedance for noise for the OPA659make it an ideal wideband,the measurement equipment load and cable.transimpedance amplifier for low to moderate Generally,data sheet voltage swing specifications are transimpedance gains.Higher transimpedance gains measured at the output pin,V OUT ,in Figure 36.

(above 100k ?)can benefit from the low input noise current of a JFET input op amp such as the OPA659.Designs that require high bandwidth from a large area detector can benefit from the low input voltage noise for the OPA659.This input voltage noise is peaked up over frequency by the diode source capacitance,and in many cases,may become the limiting factor to input sensitivity.The key elements to the design are the expected diode capacitance (C D )with the reverse bias voltage (–V B )applied,the desired transimpedance gain,R F ,and the GBP for the OPA659(350MHz).Figure 37shows a general transimpedance TIA,using the OPA659.Given the source diode capacitance plus parasitic input capacitance for the OPA659,the transimpedance gain,and known GBP,the feedback Figure 36.General Inverting Test Circuit capacitor value,C F ,may be calculated to avoid excessive peaking in the frequency response.

The inverting circuit can also use a wide range of resistor values to set the gain;Table 2lists several recommended resistor values gains with a 50?input/output match.

Table 2.Resistor Values for Inverting Gains with

50?Input/Output Match

INVERTING GAIN

R F R G R T R OUT –124924961.949.9–224912484.549.9–524949.9Open 49.9–10

499

49.9

Open

49.9

Figure 37.Wideband,Low-Noise,Transimpedance

Amplifier (TIA)

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2R C p F F

(1)

f =

-3dB (2)

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To achieve a maximally flat second-order Butterworth

turn requires a total feedback capacitance of 0.46pF.frequency response,the feedback pole should be set Typical surface mount resistors have a parasitic to:

capacitance of 0.2pF,leaving the required 0.26pF value to achieve the required feedback pole.This calculation gives an approximate 4.9MHz,–3dB bandwidth computed by:

For example,adding the common mode and differential mode input capacitance (0.7+ 2.8=3.5)pF to the diode source with the 20pF capacitance,and targeting a 100k ?transimpedance Table 3lists the calculated component values and gain using the 350MHz GBP for the OPA659,for various TIA gains and diode requires a feedback pole set to 3.44MHz.This pole in

capacitance.

Table 3.OPA659TIA Component Values and Bandwidth for Various Diode Capacitance and Gains

C DIODE =10pF

C D R F C F f –3dB 13.5pF 1k ? 3.50pF 64.24MHz 13.5pF 10k ? 1.11pF 20.31MHz 13.5pF 100k ?0.35pF 6.42MHz 13.5pF 1M ?

0.11pF

2.03MHz

C DIODE =20pF

23.5pF 1k ? 4.62pF 48.69MHz 23.5pF 10k ? 1.46pF 15.40MHz 23.5pF 100k ?0.46pF 4.87MHz 23.5pF 1M ?

0.15pF

1.54MHz

C DIODE =50pF

53.5pF 1k ? 6.98pF 32.27MHz 53.5pF 10k ? 2.21pF 10.20MHz 53.5pF 100k ?0.70pF 3.23MHz 53.5pF 1M ?

0.22pF

1.02MHz

C DIODE =100pF

103.5pF 1k ?9.70pF 23.20MHz 103.5pF 10k ? 3.07pF 7.34MHz 103.5pF 100k ?0.97pF 2.32MHz 103.5pF

1M ?

0.31pF

0.73MHz

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OPERATING SUGGESTIONS

Setting Resistor Values to Minimize Noise

Frequency Response Control

NI OPA659

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Putting high resistor values into Equation4can

quickly dominate the total

noise.A source impedance on the noninverting input The OPA659provides a very low input noise voltage.of5k?adds a Johnson voltage noise term equal to To take full advantage of this low input noise,that of the amplifier alone(8.9nV/Hz).While the JFET designers must pay careful attention to other possible input of the OPA659is ideal for high source noise contributors.Figure38shows the op amp noise impedance applications in the noninverting analysis model noise terms included.In configuration of Figure34or Figure35,both the this model,all the noise terms are taken to be noise overall by high voltage or current density terms in either nV/√Hz or source impedances.

pA/√Hz.

Voltage-feedback op amps such as the OPA659

exhibit decreasing signal bandwidth as the signal gain

increases.In theory,this relationship is described by

the gain bandwidth product(GBP)shown in the

Electrical Characteristics.Ideally,dividing the GBP by

(also called the Noise

Gain,or NG)can predict the closed-loop bandwidth.

In practice,this guideline is valid only when the phase

margin approaches90degrees,as it does in high

gain configurations.At low gains(with increased

feedback factors),most high-speed amplifiers exhibit

a more complex response with lower phase margins.

The OPA659is compensated to give a maximally-flat

frequency response at a noninverting gain of+1(see Figure38.Op Amp Noise Analysis Model

Figure34).This compensation results in a typical

bandwidth of650MHz,far exceeding that The total output spot noise voltage can be computed predicted by dividing the350MHz GBP by 1.

as the square root of the squared contributing terms Increasing the gain causes the phase margin to to the output noise voltage.This computation adds all approach90degrees and the bandwidth to more the contributing noise powers at the output by closely approach the predicted value of(GBP/NG).At superposition,then takes the square root to arrive at a gain of+10,the OPA659shows the35MHz

a spot noise voltage.Equation3shows the general bandwidth predicted using the simple formula and the

form for this output noise voltage using the terms typical GBP of350MHz.Unity-gain stable op amps shown in Figure38.such as the OPA659can also be band-limited in

gains other than+1by placing a capacitor across the

feedback resistor.For the noninverting configuration

of Figure35,a capacitor across the feedback resistor

gain with frequency down to a gain of

(3)

+1.For instance,to band-limit a gain of+2design to Dividing this expression by the noise gain(G N=1+20MHz,a32pF capacitor can be placed in parallel R F/R G)gives the equivalent input-referred spot noise with the249?feedback resistor.This configuration, voltage at the noninverting input,as Equation4however,only decreases the gain https://www.360docs.net/doc/f18715276.html,ing shows.a feedback capacitor to limit the signal bandwidth is

more effective in the inverting configuration of

Figure36.Adding that same capacitance to the

Figure36sets a pole in the signal

frequency20MHz,but in this case it

(4)

continues to attenuate the signal gain to less than1.

Note,however,that the noise gain of the circuit is

only reduced to a gain of1with the addition of the

feedback capacitor.

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Driving Capacitive Loads

Distortion Performance

OPA659

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One of the most demanding,and yet very common,

The OPA659is capable of delivering a low distortion load conditions for an op amp is capacitive loading.signal at high frequencies over a wide range of gains.The OPA659is very robust,but care should be taken The distortion plots in the Typical Characteristics with light loading scenarios so that output show the typical distortion capacitance does not decrease stability and increase conditions.Generally,until the fundamental signal closed-loop frequency response peaking when a reaches very high frequencies or powers,the second capacitive load is placed directly on the output pin.harmonic dominates the distortion with a negligible When the amplifier open-loop output resistance is third harmonic component.Focusing then on the considered,this capacitive load introduces an second harmonic,increasing the load impedance additional pole in the signal path that can decrease improves distortion directly.Remember that the total the phase margin.Several external solutions to this load includes the feedback network:in the problem have been suggested.When the primary noninverting configuration,this network is the sum of considerations are frequency response flatness,R F +R G ,while in the inverting configuration the pulse response fidelity,and/or distortion,the simplest network is only R F (see Figure 35).Increasing the and most effective solution is to isolate the capacitive output voltage swing harmonic load from the feedback loop by inserting a series distortion.A 6dB increase in output swing generally isolation resistor,R ISO ,between the amplifier output increases the second harmonic by 12dB and the third and the capacitive load.In effect,this resistor isolates harmonic by 18dB.Increasing the signal gain also the phase shift from the loop gain of the amplifier,increases the second-harmonic distortion.Again,a thus increasing the phase margin and improving 6dB increase in gain increases the second and third stability.The Typical Characteristics show the harmonics by about 6dB,even with a constant output recommended ISO and the power and frequency.Finally,the distortion increases resulting frequency response with a 1k ?load (see as the fundamental frequency increases because of Figure 24).Note that larger R ISO values are required the rolloff in the loop gain with frequency.Conversely,capacitive loading.In this case,a design the distortion improves going to lower frequencies,target of a maximally-flat frequency response was down to the dominant open-loop pole at used.Lower values of R ISO may be used if some approximately 300kHz.

peaking can be tolerated.Also,operating at higher Note that power-supply decoupling is critical for gains (instead of the +1gain used in the Typical harmonic distortion performance.In particular,for Characteristics )requires lower values of R ISO optimal second-harmonic performance,the frequency response.Parasitic power-supply high-frequency 0.1μF decoupling capacitive loads greater than 2pF can begin to capacitors to the positive and negative supply pins degrade the performance of the OPA659.Moreover,should be brought to a single point ground located long PCB traces,unmatched cables,and connections away from the input pins.

to multiple devices can easily cause this value to be exceeded.Always consider this effect carefully,and The OPA659has an extremely low third-order add the recommended series resistor as close as harmonic distortion.This characteristic also shows up possible to the OPA659output pin (see the Board in the two-tone,third-order intermodulation spurious Layout section).

(IMD3)response curves (see Figure 19).The third-order spurious levels are (less With heavier loads (for example,the 100?load than –100dBc)at low output power levels and presented in the test circuits and used for testing frequencies below 10MHz.The output stage typical characteristic performance),the OPA659is continues to hold these levels low even as the very robust;R ISO can be as low as 10?with fundamental power reaches higher levels.As with capacitive loads less than 5pF and continue to show most op amps,the spurious intermodulation powers a flat frequency response.

do not increase as predicted by a traditional intercept model.As the fundamental power level increases,the dynamic range does not decrease significantly.For two tones centered at 10MHz,with –2dBm/tone into a matched 50?load (that is,0.5V PP for each tone at the load,which requires 2V PP for the overall two-tone envelope at the output pin),the Typical Characteristics show a 96dBc difference the third-order intermodulation spurious levels.This exceptional performance improves further when operating at lower frequencies and/or higher load impedances.

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Board Layout OPA659

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device performance.Good axial metal film or

surface-mount resistors have approximately0.2pF in Achieving optimum performance with a shunt with the resistor.For resistor values greater high-frequency amplifier such as the OPA659than1.5k?,this parasitic capacitance can add a pole requires careful attention to PCB layout parasitics and and/or zero below500MHz that can affect circuit external component types.Recommendations that operation.Keep resistor values as low as possible, can optimize device performance include the consistent with load driving considerations.It is

following.recommended to keep R

F ||R

G less than250?.This

low value ensures that the resistor noise terms a)Minimize parasitic capacitance to any ac ground

remain low,and minimizes the effects of the parasitic for all of the signal input/output(I/O)pins.Parasitic

capacitance.Transimpedance applications(for capacitance on the output and inverting input pins

example,see Figure37)can use the feedback can cause instability:on the noninverting input,it can

resistor as long as the react with the source impedance to cause

feedback compensation capacitor is set given unintentional band-limiting.To reduce unwanted

consideration to all parasitic capacitance terms on the capacitance,a window around the signal I/O pins

inverting node.

should be opened in all of the ground and power

planes around those pins.Otherwise,ground and d)Connections to other wideband devices on the power planes should be unbroken elsewhere on the board may be made with short direct traces or board.through onboard transmission lines.For short

connections,consider the trace and the input to the b)Minimize the distance(less than0.25in,or

next device as a lumped capacitive load.Relatively 6,35mm)from the power-supply pins to the

wide traces(50mils to100mils,or1,27cm to2,54cm) high-frequency,0.1μF decoupling capacitors.At the

should be used.Estimate the total capacitive load device pins,the ground and power plane layout

and set R ISO from the plot of Recommended R ISO vs should not be in close proximity to the signal I/O pins.

Capacitive Load(Figure24).Low parasitic capacitive Use a single point ground,located away from the

loads(less than need an R ISO because input pins,for the positive and negative supply

the OPA659is nominally compensated to operate high-frequency,0.1μF decoupling capacitors.Avoid

with a2pF parasitic load.

narrow power and ground traces to minimize

inductance between the pins and the decoupling Higher parasitic capacitive loads without an R

ISO are

capacitors.The power-supply connections should allowed as the signal gain increases(increasing the always be decoupled with these https://www.360docs.net/doc/f18715276.html,rger unloaded phase margin).If a long trace is required, (2.2μF to10μF)decoupling capacitors,effective at and the6dB signal loss intrinsic to a lower frequencies,should also be used on the supply doubly-terminated transmission line is acceptable, pins.These larger capacitors may be placed implement a matched impedance transmission line somewhat farther from the device and may be shared using microstrip or stripline techniques(consult an among several devices in the same area of the PCB.ECL design handbook for microstrip and stripline

layout techniques).A50?environment is normally c)Careful selection and placement of external

not necessary onboard,and in fact a higher components preserves the high-frequency

impedance environment improves distortion as shown performance of the OPA659.Resistors should be a

in the distortion versus load plots.With a very low reactance type.Surface-mount resistors

characteristic board trace impedance defined based work best and allow a tighter overall layout.Metal film

on board material and trace dimensions,a matching and carbon composition,axially-leaded resistors can

series resistor into the trace from the output of the also provide good high-frequency performance.

OPA659is used as well as a terminating shunt Again,keep the leads and PCB trace length as short

resistor at the input of the destination device. as possible.Never use wirewound-type resistors in a

Remember also that the terminating impedance is the high-frequency application.The inverting input pin is

parallel combination of the shunt resistor and the the most sensitive to parasitic capacitance;

input impedance of the destination device:this total consequently,always position the feedback resistor

effective impedance should be set to match the trace as close to the negative input as possible.The output

impedance.If the6dB attenuation of a is also sensitive to parasitic capacitance;therefore,

doubly-terminated transmission line is unacceptable, position a series output resistor(in this case,R ISO)as

a long trace can be series-terminated at the source close to the output pin as possible.

end only.Treat the trace as a capacitive load in this Other network components,such as noninverting case,and set the series resistor value as shown in

input termination resistors,should also be placed the plot of R

ISO vs Capacitive Load(Figure24).This

close to the package.Even with a low parasitic configuration does not preserve as capacitance,excessively high resistor values can

create significant time constants that can degrade

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Input and ESD Protection

OPA659

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well as a doubly-terminated line.If the input

impedance of the destination device is low,there will be some signal attenuation as a result of the voltage divider formed by the series output into the terminating impedance.

e)Socketing a high-speed part such as the OPA659is not recommended.The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic Figure 39.Internal ESD Protection

network that can make it almost impossible to achieve a smooth,stable frequency response.Best These diodes provide moderate protection to input results are obtained by soldering the OPA659directly overdrive voltages above the supplies as well.The onto the board.

protection diodes can typically support 30mA continuous current.Where higher currents are possible (for example,in systems with ±12V supply The OPA659is built using a very high-speed parts driving into the OPA659),current limiting series complementary bipolar process.The internal junction resistors should be added into the two inputs.Keep breakdown voltages are relatively low for these very these resistor values as low as possible because high small geometry devices.These breakdowns are values degrade both noise performance and reflected in the Absolute Maximum Ratings table.All frequency response.

device pins are diodes to the power supplies,as Figure 39shows.

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EVALUATION MODULE

Schematic and PCB Layout

OPA659

Figure 40is the OPA659EVM https://www.360docs.net/doc/f18715276.html,yers 1through 4of the PCB are shown in Figure 41.It is to follow the layout of the external components near to the amplifier,ground and power routing as closely as possible.

Figure 40.OPA659EVM Schematic

Figure 41.OPA659EVM Layers 1through 4

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Bill of Materials

OPA659

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Table 4lists the bill of material for the OPA659EVM as supplied from TI.

Table 4.OPA659EVM Parts List

REFERENCE MANUFACTURER ITEM DESCRIPTION

SMD SIZE

DESIGNATOR

QUANTITY

PART NUMBER 1Cap,10.0μF,Tantalum,10%,35V D C1,C22(AVX)TAJ106K035R 2Cap,0.1μF,Ceramic,X7R,16V 0603C3,C42(AVX)0603YC104KAT2A

3Open 0603R1,R224Resistor,0?

0603R41(ROHM)MCR03EZPJ0005Resistor,49.9?,1/10W,1%0603

R3,R52(ROHM)MCR03EZPFX49R9Jack,Banana Receptance,0.25in

6J4,J5,J83(SPC)813

diameter hole

7Connector,Edge,SMA PCB Jack J1,J2,J33(JOHNSON)142-0701-8018Test Point,Black TP11(KEYSTONE)50019IC,OPA659

1(TI)OPA659DRB 10Standoff,4-40HEX,0.625in length 4(KEYSTONE)180811Screw,Phillips,4-40,.250in 4SHR-0440-016-SN 12Board,Printed Circuit 1(TI)EDGE#6506173(STEWARD)

Bead,Ferrite,3A,80?

1206

FB1,FB2

HI1206N800R-00

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