EDA数字时钟设计说明
Quartus数字时钟设计
1.可以快速设置时钟起始值；
2.在59分50秒时开始报时，七声低音，一声高音，报完刚好整点。
1.顶层设计（采用BDF文件图形设计，文件名：timer.bdf）
2.秒计时器模块设计
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity second1 is
port(clk1s:in std_logic;
reset:in std_logic;
sec2,sec1:buffer std_logic_vector(3 downto 0);--秒的十位和个位 seco: out std_logic); --秒计时器的进位输出end;
architecture A of second1 is
begin
process(clk1s,reset)
begin
if reset = '0' then
sec2 <= "0000"; sec1 <= "0000"; --清零秒计时器
seco <= '0';
elsif clk1s'event and clk1s ='1' then
if (sec1 = "1001" and sec2 = "0101") then
sec2 <= "0000";sec1 <="0000"; --在59秒时回零
seco <= '1'; --进位
elsif (sec1 ="1001") then
sec1 <="0000";
sec2 <= sec2+1;
seco <= '0';
else
sec1 <= sec1+1;
seco <= '0';
end if;
end if;
end process;
end;
3.分计时器模块设计
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity minute1 is
port(clkm,clk1s,setm:in std_logic; --秒进位输入，1HZ校分时钟输入信号，校分控制信号
min2,min1:buffer std_logic_vector(3 downto 0); --分计时器的十位和个位
minco:out std_logic);
end;
architecture A of minute1 is
signal clkx:std_logic;
begin
Pclkm:process(clkm,clk1s,setm)
begin --根据是否校分选择计时时钟
if setm ='1' then clkx <= clk1s; --利用clk1s信号对分的初值进行快速设置
else clkx <=clkm; --利用秒的进位信号正常计时
end if;
end process;
Pcontm:process(clkx)
begin
if clkx'event and clkx ='1' then
if (min1 = "1001" and min2 = "0101") then
min1 <="0000";min2 <="0000";minco <='1'; --59分时回零并进位
elsif (min1 = "1001") then
min1 <="0000";min2 <= min2+1;
minco <= '0';
else
min1 <= min1+1;minco <='0';
end if;
end if;
end process;
end;
4.时计时器模块设计
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity hour1 is
port(clkh,clk1s,seth:in std_logic;
hou2,hou1:buffer std_logic_vector(3 downto 0) ); --时的十位和个位
end;
architecture A of hour1 is
signal clky:std_logic;
begin
Pclkh:process(clkh,clk1s,seth)
Begin --根据是否校时选择计时时钟
if seth ='1' then clky <=clk1s; --利用clk1s信号对时的初值进行快速设置 else clky <= clkh; --利用分的进位信号正常计时
end if;
end process;
Pconth:process(clky)
begin
if clky'event and clky ='1' then
if (hou1="0011" and hou2 ="0010" ) then
hou1 <= "0000";hou2 <= "0000"; --23时回零
elsif (hou1 ="1001") then
hou1 <= "0000";
hou2 <= hou2+1;
else
hou1 <= hou1+1;
end if;
end if;
end process;
end;
5.报时模块设计
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity alarm1 is
port(clk1s,clk500,clk1k: in std_logic;
sec2,sec1,min2,min1: in std_logic_vector(3 downto 0);
alarm: out std_logic);
end;
architecture A of alarm1 is
begin
process(clk1s)
variable flag500:std_logic;variable flag1k:std_logic;
begin
if clk1s'event and clk1s = '1' then
if(min1 ="1001" and min2="0101" and sec2="0101" ) then --59分50秒时开始报时
case sec1 is
when "0000" => flag500:='1';
when "0010" => flag500:='1';
when "0100" => flag500:='1';
when "0110" => flag500:='1';
when "0111" => flag500:='1';
when "1000" => flag500:='1';
when "1001" => flag500:='1'; --50,52,54,56,58,59秒时低频率报时
when others => flag500:='0';flag1k:='0';
end case;
else flag500:='0';flag1k:='0';
end if;
if (min1 ="0000" and min2="0000" and sec1="0000" and sec2="0000") then
flag1k:='1'; --整点时高频率报时
end if;
end if;
if flag500='1' then alarm <=clk500;
elsif flag1k='1' then alarm <=clk1k;
else alarm <='0';
end if;
end process;
end;
三.仿真结果
1.秒计时器仿真结果
2.分计时器仿真结果
3.时计时器仿真结果
4.报时模块仿真结果