8位乘法器实验报告

6.2 8位乘法器的设计

1.实验目的

（1）熟悉isEXPERT/MAX+plusisEXPERT/MAX+plus II/Foudation Series 软件的基本使用方法。

（2）熟悉GW48-CK EDA实验开发系统的基本使用方法。

（3）学习VHDL基本逻辑电路的综合设计。

2．实验内容

设计并调试好由8位加法器构成的以时序逻辑方式设计的8位乘法器。此乘法器通过判断被乘数的位值为1还是零，并通过乘数的左移与上一次和相加的方法，实现了8位乘法的运算，并用GW48-CK EDA实验开发系统进行硬件验证。

3.实验条件

（1）开发设备：Lattice ispEXPERT。

（2）实验设备：GW48-CK EDA实验开发系统。

（3）拟用芯片：ispLSI1032E PLCC-84或EPF10K10LC84-3或XCS05/XL PLCC84以及运算控制电路和外部时钟。

4.实验设计

1）系统的原理框图

2）VHDL源程序

（1）选通与门模块的源程序ANDARITH.VHD

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY ANDARITH IS

PORT(ABIN: IN STD_LOGIC;

DIN: IN STD_LOGIC_VECTOR(7 DOWNTO 0); DOUT: OUT STD_LOGIC_vector(7 DOWNTO 0)); END ENTITY ANDARITH;

ARCHITECTURE ART OF ANDARITH IS

BEGIN

PROCESS(ABIN,DIN)IS

BEGIN

FOR I IN 0 TO 7 LOOP

DOUT(I)<=DIN(I)AND ABIN;

END LOOP;

END PROCESS;

END ARCHITECTURE ART;

(2)16位锁存器的源程序REG16B.VHD LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY REG16B IS

PORT (CLK: IN STD_LOGIC;

CLR: IN STD_LOGIC;

D: IN STD_LOGIC_VECTOR(8 DOWNTO 0); Q: OUT STD_LOGIC_VECTOR(15 DOWNTO 0)); END ENTITY REG16B;

ARCHITECTURE ART OF REG16B IS

SIGNAL R16S: STD_LOGIC_VECTOR(15 DOWNTO 0); BEGIN

PROCESS(CLK,CLR)IS

BEGIN

IF CLR='1' THEN R16S<="0000000000000000"; ELSIF CLK'EVENT AND CLK= '1' THEN

R16S(6 DOWNTO 0)<=R16S(7 DOWNTO 1);

R16S(15 DOWNTO 7)<=D;

END IF;

END PROCESS;

Q<=R16S;

END ARCHITECTURE ART;

(3)8位右移寄存器的源程序SREG8B.VHD

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY SREG8B IS

PORT(CLK:IN STD_LOGIC; LOAD:IN STD_LOGIC; DIN:IN STD_LOGIC_VECTOR(7 DOWNTO 0); QB: OUT STD_LOGIC);

END ENTITY SREG8B;

ARCHITECTURE ART OF SREG8B IS

SIGNAL REG8B :STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN

PROCESS(CLK, LOAD)IS

BEGIN

IF CLK'EVENT AND CLK='1'THEN

IF LOAD='1'THEN REG8B<=DIN;

ELSE REG8B(6 DOWNTO 0)<=REG8B(7 DOWNTO 1); END IF;

END IF;

END PROCESS;

QB<=REG8B(0);

END ARCHITECTURE ART;

(4)乘法运算控制器的源程序ARICTL.VHD

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY ARICTL IS

PORT(CLK:IN STD_LOGIC; START:IN STD_LOGIC; ARIEND:OUT STD_LOGIC;

CLKOUT: OUT STD_LOGIC;

RSTALL: OUT STD_LOGIC);

END ENTITY ARICTL;

ARCHITECTURE ART OF ARICTL IS

SIGNAL CNT4B: STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN

RSTALL<=START;

PROCESS(CLK,START)IS

BEGIN

IF START='1'THEN CNT4B<="0000";

ELSIF CLK'EVENT AND CLK='1'THEN

IF CNT4B<8 THEN

CNT4B <=CNT4B+1;

END IF;

END IF;

END PROCESS;

PROCESS(CLK,CNT4B,START)IS

BEGIN

IF START='0' THEN

IF CNT4B<8 THEN

CLKOUT <=CLK;ARIEND<='0';

ELSE CLKOUT<='0';ARIEND<='1';

END IF;

ELSE CLKOUT<=CLK;ARIEND<='0';

END IF;

END PROCESS;

END ARCHITECTURE ART;

(5)8位乘法器的源程序MULTI8X8.VHD

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY MULTI8X8 IS

PORT(CLK:IN STD_LOGIC;

START:IN STD_LOGIC;

A:IN STD_LOGIC_VECTOR(7 DOWNTO 0);

B:IN STD_LOGIC_VECTOR(7 DOWNTO 0);

ARIEND:OUT STD_LOGIC;

DOUT:OUT STD_LOGIC_VECTOR(15 DOWNTO 0)); END ENTITY MULTI8X8;

ARCHITECTURE ART OF MULTI8X8 IS

COMPONENT ARICTL IS

PORT(CLK:IN STD_LOGIC;START:IN STD_LOGIC;

CLKOUT:OUT STD_LOGIC; RSTALL:OUT STD_LOGIC; ARIEND: OUT STD_LOGIC);

END COMPONENT ARICTL;

COMPONENT ANDARITH IS

PORT(ABIN:IN STD_LOGIC;

DIN:IN STD_LOGIC_VECTOR(7 DOWNTO 0);

DOUT: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END COMPONENT ANDARITH;

COMPONENT ADDER8B IS

PORT(CIN: IN STD_LOGIC;

A: IN STD_LOGIC_VECTOR(7 DOWNTO 0);

B: IN STD_LOGIC_VECTOR(7 DOWNTO 0);

S: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);

COUT: OUT STD_LOGIC);

END COMPONENT ADDER8B ;

COMPONENT SREG8B IS

PORT(CLK: IN STD_LOGIC;

LOAD: IN STD_LOGIC;

DIN: IN STD_LOGIC_VECTOR(7 DOWNTO 0);

QB: OUT STD_LOGIC);

END COMPONENT SREG8B ;

COMPONENT REG16B IS

PORT (CLK: IN STD_LOGIC;

CLR: IN STD_LOGIC;

D: IN STD_LOGIC_VECTOR(8 DOWNTO 0);

Q: OUT STD_LOGIC_VECTOR(15 DOWNTO 0)); END COMPONENT REG16B ;

SIGNAL S1: STD_LOGIC;

SIGNAL S2: STD_LOGIC;

SIGNAL S3: STD_LOGIC;

SIGNAL S4: STD_LOGIC;

SIGNAL S5: STD_LOGIC_VECTOR(7 DOWNTO 0);

SIGNAL S6: STD_LOGIC_VECTOR(8 DOWNTO 0);

SIGNAL S7: STD_LOGIC_VECTOR(15 DOWNTO 0);

BEGIN

DOUT<=S7; S1<='0';

U1:ARICTL PORT MAP(CLK=>CLK,START=>START,

CLKOUT=>S2,RSTALL=>S3,ARIEND=>ARIEND);

U2:SREG8B PORT MAP(CLK=>S2,LOAD=>S3,

DIN=>A,QB=>S4);

U3:ANDARITH PORT MAP(ABIN=>S4,DIN=>B,DOUT=>S5);

U4:ADDER8B PORT MAP(CIN=>S1,A=>S7(15 DOWNTO 8)),

B=>S5(7 DOWNTO 0),S=>S6(7 DOWNTO 0),COUT=>S6(8); U5:REG16B PORT MAP(CLK=>S2,CLR=>S3,D=>S6(8 DOWNTO 0),Q=>S7(7 DOWNTO 0));

END ARCHITECTURE ART;

5.系统仿真文件

当ATRRT为高电平时，将16位寄存器清零，当START为低电平时，在CLK为1时进行乘法运算，通过8次移位和加法操作，运算进行8个CLK为1的时钟，之后得到输出结果，且ARIEND为1,乘法运算结束。

6.实验小结

本实验有点复杂，代码比较多，很容易在敲代码时出错，这个实验使我懂得做事要认真，要有耐心。本实验在仿真时不太顺利，当仿真出一个结果时，再修改输入时，多修改两次就不能出结果，要不结果就不正确，关闭软件再开启，再仿真又可以得出正确结果，不知道怎么回事，和同学研究也没得结果。