乘法器VERILOG

Advances in Computational Sciences and Technology

ISSN 0973-6107 Volume 3 Number 2 (2010) pp. 223–235

? Research India Publications

https://www.360docs.net/doc/cc16950438.html,/acst.htm

Run-Time Reconfigurable Pipelined Modified

Baugh-Wooley Multipliers

Aswathy Sudhakar1 and D. Gokila2

1,2VLSI Design Group, Department of Electronics and Communication Engineering Amrita School of Engineering, Amrita Vishwa Vidyapeetham,

Coimbatore-641105, India

E-mal:1achu1921@https://www.360docs.net/doc/cc16950438.html,, 2d_gokila@https://www.360docs.net/doc/cc16950438.html,

Abstract

FPGA implementation of multipliers causes area overhead problem since they are implemented separately with separate functionalities even if they are to perform the same calculation. This also causes increased power dissipation.

Also FPGA device sizes can only increase as fast as the silicon process technology will allow it to. The multiplier redundancy can be removed by Run-Time Reconfiguration which is the very best solution for reducing FPGA area thereby reducing the power consumption. In this paper, the basic structure of the Baugh-Wooley (BW) multiplier, which is proved to be the best suitable choice for multiplier reconfiguration is modified for optimizing constraints like speed, area, accuracy and power consumption. The reconfiguration on Baugh-Wooley multiplier is explained with respect to the optimum reconfiguration constraints. Various techniques like pipelining, true rounding, 2-D pipeline gating are effectively incorporated in the modified BW multiplier design to optimize the constraints. The large speed overhead caused by reconfiguration limits it from practical applications which are overcome by using pipeline registers. Effective use of pipeline registers is made so as to control the speed overhead problem occurring through the reconfiguration of multiplier functionalities. The results are compared between non-reconfigurable, non-reconfigurable pipelined and reconfigurable 8-stage pipelined modified BW multiplier architectures for n=8, 16, 32, and 64. It is obtained that the Partial Run-Time Reconfiguration reduces the area by 31-40%. Pipelining improves the speed by 4-5 times whereas run-time reconfiguration results in 2-5% reduction in overall power dissipation.

224 Aswathy Sudhakar and D. Gokila Keywords: Run-Time Reconfiguration, Baugh-Wooley Multiplier, Fixed-

Width Multiplier, Reconfiguration Speed, Sub-Word Multiplication, 2-D Pipeline Gating and Pipeline Register.

Introduction

Digital designs can be implemented on a configurable logic platform provided by FPGAs. The designs based on FPGAs are beginning to dominate in almost all fields due to various advantages like simplicity, portability, high performance and low power dissipation and as the complexity relentlessly increases, FPGAs are beginning to be used in application domains requiring intensive arithmetic operations, such as signal processing. FPGAs are now-a-days technologically evolved and complex that they are able to host an entire system-on-chip. Recent advances in VLSI technology provide very complex digital-signal-processing algorithms to be cost effectively implemented. But at the same time, the design complexity to achieve high-speed performance, reduced area and power efficiency becomes a major challenge. FPGAs are very costly in terms of area occupation and more importantly in terms of power consumption. Also a multi-million gate FPGA era is expected. Power consumption in a chip increases due to increase in the number of gates and also due to the implementation of redundant modules serving the same functionality repeatedly. It also increases the heat loss which results in device damage. A very effective solution consists of reconfiguration of FPGAs.

Reconfiguration of multipliers in an FPGA reduces the power dissipation as well as area overhead mainly by limiting the number of redundant modules. There are two levels of reconfiguration architecture [1]: design-time (static configuration of some architectural parameters) and at run-time (dynamic reconfiguration of the overall functionality or algorithm implemented by the array). Dynamic reconfiguration is heavily used to implement a given computation, and it is utilized to exploit time multiplexing of the FPGA resources and ensure software-oriented flexibility of the cells. Dynamic or run-time reconfiguration (RTR) [1] is defined as the ability to change or modify the functional configuration of a device on the fly. For practically any DSP system, multiplication is a vital function. The reconfiguration of multiplier blocks is thus taken into consideration to improve the reconfiguration constraints. The various multiplier types based on architectures [2, 3, 4], introduced necessitates the need for an efficient multiplier selection for a particular function. From the comparisons, the Baugh-Wooley Multiplier is the power and area efficient one and is the best suited choice for reconfiguration due to high-speed and regularity in the architecture. Reconfiguration of BW multipliers [5] keeping n+w most significant columns [6, 10] is performed for reducing the power dissipation. But this generates accuracy reduction in low-resolution fixed-width multiplication caused by the redundant bits in the sign-extension circuit and limits its reconfiguration efficiency. In [7], the presented work reduced the accuracy degradation in fixed-width multipliers by truncation with rounding technique which has accuracy almost equal to the rounding technique with a little circuit complexity. With the 2-D pipeline gating [8] technique in the Baugh-Wooley reconfigurable multiplier, the low-resolution errors

Run-Time Reconfigurable Pipelined Modified 225 are minimized as it improves the regularity of the computing architecture. But this has area overhead and increased redundancy and are minimized in [9] by the sub-word multiplication technique. Here the limited pipelining structures fail to achieve high speed and 2-D pipeline gating causes timing mismatch which leads to increased latency. In [11], a BW multiplier which included techniques to save the power consumption with truncated multiplication. This has poor accuracy and increased redundancy. In [12], the accuracy degrades due to variation in the co-ordination of processing of bits in the input samples. So for almost all the techniques discussed, the implementations causes the reconfiguration overhead which results in a huge decrease in speed due to increased latency and hence making reconfiguration practically difficult.

In this paper, the best suited multiplier for reconfiguration, the Baugh-Wooley multiplier architecture is modified to make it suitable for reconfiguration among three arithmetic functions. The three configuration modes (CM) include: 1) n x n fixed-width multiplier 2) two n/2 x n/2 fixed-width multipliers 3) n/2 x n/2 full-precision multiplier. The constraints taken into consideration for optimization are Power Dissipation, Area, Speed and Accuracy. Various methods like pipelining, reconfiguration, true rounding, 2-D pipelining etc are incorporated in the modified BW architecture to optimize these performance constraints and to overcome the huge reconfiguration overhead in speed. Also a comparison is made between non-reconfigurable, non-reconfigurable pipelined and reconfigurable pipelined modified BW multipliers for n=8, 16, 32, and 64.

The rest of the paper is organized as follows. The modified BW Multiplier design is explained in Section 2. Section 3 gives the design of reconfigurable modified BW multiplier with optimum constraints. In Section 4, implementation results in terms of power, area and speed and comparisons are presented. Section 5 concludes the paper. Modified Baugh Wooley (BW) Multiplier Design

Pipelined modified BW multiplier design for n=8 is shown in Figure 1(a). The techniques added with the conventional BW multiplier are pipelining, truncation with rounding and 2-D pipelining. The pipelining effect in multiplication is shown in Figure 1(b). The registers are placed in between various multiplication stages according to the functionality required. These registers are termed as pipeline registers. The same technique is used for modifying the basic multiplier design to improve the speed. As in Figure 1(a), the partial product bits created are stored in the pipeline registers. After segregation of partial products pipeline registers follows the partial product block. This avoids the delay and the latency caused by the two’s complement calculation. When pipeline registers are used here in the design, the blocks following pipeline register access input from the register so that the preceding blocks can operate on successive data. This considerably improves the processing time of a large amount of successive input data. Pipelining ensures the partial product bits to be ready for summation simultaneously so that the errors due to latency can be removed. Latency causes the error to be propagated to the next stages of calculations. Pipelined registers are used to decrease the delay, thereby improving the speed. Here

226 Aswathy Sudhakar and D. Gokila the multiplier module itself is pipelined along with the pipelined reconfigurable structure.

True rounding or Truncation with Rounding of the partial products [8] improves the accuracy of the final output also with reduced power dissipation. True Rounding requires adding a ‘1’ at the n th least significant bit position of the product which helps to control the possible errors while truncation is performed. After segregation, the negative partial products are inverted and added to the positive partial products. The inversion is done by 2-D pipelining [7] to maintain the regularity in the design. The addition of partial products thus formed gives the final product. This design has considerable increase in speed due to pipelining and accuracy improvement due to true rounding.

(a) (b) Figure 1. (a)Efficient fixed-width modified BW multiplier for n=8; (b) Pipelining in Multiplication.

Design of Reconfigurable Modified BW Multiplier for Optimum Constraints

The performance constraints taken into consideration here are: 1) Power Dissipation, 2) Area, and 3) Speed. The partial product array diagram for an nxn modified BW multiplier is shown in Figure 2. Figure 2(a) shows the generalized product diagram and 2(b) shows that for n=8. Figure 2(c) shows the partial products remaining after truncation for design. Here the LSBs are masked by truncation. The ‘w’ bit decides the length of the output product. In this design ‘w=1’ is taken.

Run-Time Reconfigurable Pipelined Modified 227

(a)

(b) (c)

Figure 2: (a) Partial Product Array Diagram for an n-bit modified BW Multiplier, (b) Partial Product Array Diagram for an 8-bit modified BW Multiplier and (c) Partial products after truncation.

Figure 3: Design of reconfigurable modules (MUL1, MUL2 and MUL3).

The modules are defined by the sub-word multiplication technique [6] as shown in Figure 4. Here X [x7 x6 ……x0] and Y [y7 y6 ……y0 ] are the two 8-bit inputs. The sub-words are X1[x7 x6 x5 x4] , X0[x3 x2 x1 x0], Y1[y7 y6 y5 y4] and Y0[x3 x2 x1 x0]. It is clear from the design that MUL1 and MUL2 modules perform the fixed-width 4x4 multiplication and MUL module performs the full-precision 4x4 multiplication. This can be used for the reconfiguration between the functionalities.

228 Aswathy Sudhakar and D. Gokila

Figure 4: Sub-word multiplication (a) two n/2xn/2 multiplications (b) two n/2xn/2 partial-product array distribution.

CM1: nxn fixed-width multiplier

For an nxn multiplier, all the three reconfiguration modules are required and is shown in Figure 5(a). CM1 is taken as the prototype structure for reconfiguration after removal of LSBs as in Figure 5(b). Various configuration parameters (CP0, CP1, and CP2) are given with the reconfiguration modules so as to get the complete reconfiguration functionalities. These parameters combine with other settings to generate the corresponding functionalities. In CM1, CP0 and CP1 are set to ‘1’ and CP2 is set to ‘0’ as shown in Figure 5(c).

(a) (b) (c)

Figure 5. (a) CM1 array diagram, (b) Prototype Structure (c) Configuration parameter settings for CM1.

CM2: two n/2 x n/2 fixed-width multipliers

Configuration mode plays a role of performing two n/2 x n/2 fixed-width multiplications. In this, two copies of hardware resources are required to implement

Run-Time Reconfigurable Pipelined Modified 229 CM2. As described earlier, both MUL1 and MUL2 perform the n/2 x n/2 fixed-width multiplications and can be used. Here X1Y0 and X0Y1 are the n/2 –bit multiplications performed as shown in Figure 6(a). The configuration parameters CP0 and CP1 are set to ‘0’ and CP2 is set to ‘1’ as shown in Figure 6(b).

(a) (b)

Figure 6: (a) CM2 array diagram (b) Configuration parameter settings for CM2. CM3: n/2 x n/2 full-precision multiplier

With the minimum number of modules and partial product settings as the parameters, it is clear that MUL3 is the best suited for n/2 x n/2 full-precision multiplication. Figure 7(a) shows MUL3 as n/2 x n/2 full-precision multiplier and Figure 7(b) shows the corresponding configuration parameter settings where CP3 and CP4 are set to 1 and 0 respectively.

(a) (b)

Figure 7: (a) CM3 array diagram (b) Configuration parameter settings for CM3.

The proposed pipelined reconfigurable modified BW multiplier for n=8 is shown in Figure 8(d). According to the reconfiguration parameters required, reconfiguration modules are selected with the help of a decoder and the corresponding functionality is mapped on to the prototype structure. Here MUX and ADD in Figure 8(d) represent multiplexers and adders respectively. The MUL1 and MUL2 are required for both

230 Aswathy Sudhakar and D. Gokila CM1 and CM2 functionalities and so this is represented by t [2]. MUL3 is represented by t [1:0] and needed for CM1 and CM3. A decoder circuit is used to decode these select bit values. As shown in the figure, t [2] is the select bit for first MUX and t[3] is the select bit for the second MUX. The system works as: during CM1; all the three multiplier modules are required as shown in the Figure 8(c). The corresponding decoder values shows that t [3] is set to ‘1’ and t[2] is set to ‘0’ as in Figure 8(b). Hence the first MUX produces MUL3 as output. ADD1 adds the MUL1 and MUL2 outputs. Both these results are then added in ADD2. The second multiplexer selects this as the output since the select bit t [3]= ‘1’. This gives the n-bit fixed-width multiplication output (CM1). During CM2, first MUX produces the concatenated output from MUL1 and MUL2. The second MUX selects this as the output since the select bit t [3] = ‘0’. Thus two n/2-bit fixed-width multiplications can be performed by CM2. During CM3, t [3] and t [2] are 0 and MUL3 output is directly transferred to the output giving n/2 x n/2 full-precision multiplication. The pipeline registers serves the basic functionality of improving the speed by processing successive data without latency. Here 8-stage pipelining is incorporated in this design. Thus reconfiguration makes the architecture power-efficient and area-efficient where as pipelining improves the speed. The true rounding and 2-D pipelining is also incorporated in the above design practically to improve the accuracy though it is not shown.

(d)

Figure 8: (a) Configuration Parameters, (b) Truth Table of Decoder, (c) Configuration Parameter Settings, and (d) Proposed Pipelined Reconfigurable Modified BW Multiplier Architecture.

Run-Time Reconfigurable Pipelined Modified 231 Implementation Results and Comparisons

The implementation is done in Verilog HDL and logic simulation is done in ModelSim Simulator 6.2 and the synthesis is done using Altera Quartus II 7.2. The comparison between various multiplier architectures (4-bit) differentiated according to the architecture is shown in Table 1. From Table 1(a) and 1(b) it is clear that the Baugh-Wooley multiplier architecture is the best suited for reconfiguration of FPGAs. Also it is clear that the pipelining stages as in Figure 9 improve the speed by 6% with negligible increase in power in 4-bit Baugh-Wooley multiplier architecture. So in order to reduce the reconfiguration overhead in speed, pipelining can be used to improve the speed. Also reconfiguration in pipelined multipliers reduces the area overhead due to pipeline registers.

Table 1(a). Area, Speed, and Power Dissipation for various non-pipelined multiplier architectures (4-bit).

Multiplier Architecture Number

of LUTs

Clock-Period

(ns)

Speed (MHz) Power Dissipation

(mW)

Wallace Tree 34 15.852 63.08 68.52

Booth 42 16.318 61.28 67.98

Baugh-

Wooley

28 15.861 63.03 67.84

Table 1(b). Area, Speed, and Power Dissipation for various pipelined multiplier architectures (4-bit).

Multiplier Architecture Number

of LUTs

Clock-Period

(ns)

Speed (MHz) Power Dissipation

(mW)

Wallace Tree 56 15.026 66.55 68.82

Booth 60 16.012 62.45 68.16

Baugh-Wooley 32 15.029 66.53 67.97

Figure 9: Speed Comparison between various pipelined and non-pipelined multiplier architectures (4-bit).

232 Aswathy Sudhakar and D. Gokila The synthesis results of non-reconfigurable modified BW multiplier, reconfigurable modified BW multiplier, and non-reconfigurable pipelined and pipelined reconfigurable modified BW multipliers are shown in Table 2 and Table 3. From Table 2(a), it is clear that pipelining improves the speed of a non-reconfigurable modified BW multiplier by 4-5 times for various values of n whereas considerable area overhead caused by pipelining is reduced by reconfiguring the architecture. From Table 2 it is clear that for ‘n’ value greater than 32 the design is optimized.

Table 2(a): Area and Speed comparison between Non-Reconfigurable and Reconfigurable Modified BW Multiplier.

Table 2(b): Area and Speed comparison between Non-Reconfigurable Pipelined and Pipelined Reconfigurable Modified BW Multiplier.

Run-Time Reconfigurable Pipelined Modified 233 By making the system reconfigurable we can reduce the area overhead problem as shown in Table 2(a). Area reduces to 31-40 % with only a slight degradation in speed (2-6 %) caused by reconfiguration time overhead which is negligible when compared to the added advantages of pipelining. As a result the pipelining and reconfiguration together gives an improvement of 18-28 % improvement in speed when compared with non-reconfigurable non-pipelined architecture.

From Table 2(a) and 2(b), it is clear that as the number of bits increases the area can be optimized. So the design is well suited for higher input bits. Table 3 shows the power dissipation comparison between various non-reconfigurable, non-reconfigurable pipelined and reconfigurable pipelined architectures for n=8, 16, 32, and 64. In general from table 3(a), it is seen that the reconfiguration produces a reduction in power by 2-11 % in non-pipelined structures whereas the reconfiguration in the pipelined structure improves the power dissipation by 2-5 % as shown in table 3(b). Hence the overall power dissipation decreases after pipelining and reconfiguration by about 2-5%. Here also it is clear from Table 3(a) and 3(b) that as the value of ‘n’ increases the power dissipation can be compared for pipelined and non-pipelined structures and the design becomes power optimized. From the results it is clear that pipelining increases the speed by 6% in a 4-bit Baugh-Wooley multiplier and the optimization of constraints with pipelining and reconfiguration gives about 2-5% reduction in power dissipation, 4-5 times increase in speed and area reduces by 31-40% by reconfiguration. Thus the large speed overhead due to reconfiguration is controlled with the effective use of pipelining.

Table 3(a): Power Dissipation Comparison between Non-Reconfigurable and Reconfigurable Modified BW Multiplier.

234 Aswathy Sudhakar and D. Gokila Table 3(b): Power Dissipation Comparison between Non-Reconfigurable Pipelined and Pipelined Reconfigurable BW Multiplier.

Conclusion

In this paper the BW multiplier architecture has been modified and Dynamic Reconfiguration has been implemented for optimizing the reconfiguration constraints like speed, area, accuracy and power consumption. Various techniques like pipelining, true rounding, 2-D pipeline gating have been effectively incorporated in the modified BW multiplier design to optimize the constraints. Pipelined registers have been used to overcome the large speed overhead caused by reconfiguration limits it from practical applications. An improvement in speed is shown with the modification of basic Baugh-Wooley multiplier architecture making it suitable for reconfiguration. Comparisons are done between the results obtained for non-reconfigurable, non-reconfigurable pipelined and pipelined reconfigurable modified BW multiplier architectures for n=8, 16, 32, and 64. Pipelining improves the speed by 4-5 times whereas run-time reconfiguration results in 2-5% reduction in overall power dissipation. Area reduces to 31-40% in pipelined reconfigurable architecture when compared to the non-reconfigurable pipelined architectures.

References

[1][White Paper] “ALTERA: FPGA run-time reconfiguration two approaches”.

[2]Sadiq M. Sait, Aamir A. Farooqui and Gerhard. F. Beckhoff; “A Novel

Technique for Fast Multiplication” IEEE International Conference on computers and Communications on March 1995.

[3] A. Habibi and P. A. Wintz, "Fast multipliers," IEEE Trans. Comput., vol. C-

19, pp. 153-157, Feb. 1970.

[4]R. GNANASEKARAN; “A Fast Serial-Parallel Binary Multiplier”; IEEE

Transactions On Computers, Vol. C-34, No. 8, August 1985C. R. Baugh and

Run-Time Reconfigurable Pipelined Modified 235

B. A. Wooley, “A two’s complement parallel array multiplication algorithm,”

IEEE Trans. Compt., vol. C-22, no. 12, pp.1045-1047, Dec. 1973.

[5] C. R. Baugh and B. A. Wooley, “A two’s complement parallel array

multiplication algorithm,” IEEE Trans. Compt., vol. C-22, no. 12, pp.1045-

1047, Dec. 1973.

[6]Schulte, M.J., Stine, J.E., and Jansen, J.G.: ‘Reduced power dissipation

through truncated multiplication’. Proc. IEEE Alessandro Volta Memorial Workshop on Low-Power Design, 1999, pp. 61 2 69.

[7] E.E.Swartzlander, Jr., “Truncated multiplication with approximate rounding,”

in Proc. 33rd Asilomar Conference on Signals, Systems, and Computers, 1999,

vol. 2, pp. 1480-1483.

[8]J. Di and J. S. Yuan, “Run-time reconfigurable power-aware pipelined signed

array multiplier design,” in Proc. IEEE International Symposium on Signals, Circuits, and Systems, July 2003, vol. 2, pp. 405-406.

[9]S. Krithivasan, M. J. Schulte, and J. Glossner, “A sub word-parallel

multiplication and sum- of-squares unit,” IEEE Comp. society Annual Symposium on VLSI, pp. 273-274, Feb. 2004.

[10]L. D. Van and C. C. Yang, “Generalized low-error area-efficient fixed-width

multipliers,” IEEE Trans. Circuits Syst. I, vol. 52, pp. 1608-1619, Aug. 2005 [11]S.R.Kuang and J.P.Wang , “Design of power-efficient pipelined truncated

multipliers with various output precision”, IET Computers and Digital Techniques,vol.1,pp.129-136,Mar.2007.

[12]Tu, J Van, L ,“ Power-Efficient Pipelined Reconfigurable Fixed-Width Baugh-

Wooley Multipliers” ,IEEE Transactions on Computers : vol.58,pp.1346-1355,

Oct. 2009.