Bt656_receiver

//(c) 2004 Altera Corporation. All rights reserved.

//----------------------------------------------------------------
// BT656 Receiver
//----------------------------------------------------------------
`timescale 1ns/1ns

module bt656_rx (
clk,
reset_n,

din,

clk_135_en,
v_blank,
field,
pixel,
line,
y,
cb,
cr
);

input clk; // 27 MHz
input reset_n;

input [7:0] din;

output clk_135_en;
output v_blank;
output field;
output [9:0] pixel;
output [8:0] line;
output [7:0] y;
output [7:0] cb;
output [7:0] cr;

//---------------------------------------------------------------------------
// Scan input stream to decode timing reference signals
//---------------------------------------------------------------------------
reg [1:0] time_ref;
parameter idle = 2'b00,
ff = 2'b01,
ff00 = 2'b10,
ff0000 = 2'b11;

always @(posedge clk or negedge reset_n)
if (~reset_n)
time_ref <= idle;
else
case (time_ref)
idle:
if (din == 8'hff)
time_ref <= ff;

ff:
if (din == 8'h0)
time_ref <= ff00;
else
time_ref <= idle;

ff00:
if (din == 8'h0)
time_ref <= ff0000;
else
time_ref <= idle;

ff0000:
time_ref <= idle;
endcase

wire timing_ref = (time_ref == ff0000);

reg timing_ref_r;
always @(posedge clk or negedge reset_n)
if (~reset_n)
timing_ref_r <= 1'b0;
else
timing_ref_r <= timing_ref;

//---------------------------------------------------------------------------
// blanking flags
//---------------------------------------------------------------------------
reg field;
reg v;
reg h;

always @(posedge clk or negedge reset_n)
if (~reset_n)
field <= 1'b0;
else if (timing_ref)
field <= din[6];

always @(posedge clk or negedge reset_n)
if (~reset_n)
v <= 1'b0;
else if (timing_ref)
v <= din[5];

wire v_blank = v;

always @(posedge clk or negedge reset_n)
if (~reset_n)
h <= 1'b0;
else if (timing_ref)
h <= din[4];

//---------------------------------------------------------------------------
// Input capture registers
//---------------------------------------------------------------------------
reg [1:0] input_phase;
always @(posedge clk or negedge reset_n)
if (~reset_n)
input_phase <= 2'b0;
else if (h | v)
input_phase <= 2'b0;
else
input_phase <= input_phase + 2'b01;

reg [7:0] y_reg;
always @(posedge clk or negedge reset_n)
if (~reset_n)
y_reg <= 8'b0;
else if (input_phase[0])
y_reg <= din;

reg [7:0] cb_reg;
always @(posedge clk or negedge reset_n)
if (~reset_n)
cb_reg <= 8'b0;
else if (input_phase == 2'b00)
cb_reg <= din;

reg [7:0] cr_reg;

always @(posedge clk or negedge reset_n)
if (~reset_n)
cr_reg <= 8'b0;
else if (input_phase == 2'b10)
cr_reg <= din;

reg [7:0] y;
reg sav;
always @(posedge clk or negedge reset_n)
if (~reset_n)
y <= 8'b0;
else if (input_phase[0] & ~sav & ~timing_ref)
y <= y_reg;

reg [7:0] cb;
always @(posedge clk or negedge reset_n)
if (~reset_n)
cb <= 8'b0;
else if ((input_phase == 2'b11) & ~timing_ref)
cb <= cb_reg;

reg [7:0] cr;
always @(posedge clk or negedge reset_n)
if (~reset_n)
cr <= 8'b0;
else if ((input_phase == 2'b11) & ~timing_ref)
cr <= cr_reg;

always @(posedge clk or negedge reset_n)
if (~reset_n)
sav <= 1'b0;
else if (timing_ref & ((din == 8'h80) | (din == 8'hc7)))
sav <= 1'b1;
else if (input_phase == 2'b10)
sav <= 1'b0;

reg clk_135_en;
always @(posedge clk or negedge reset_n)
if (~reset_n)
clk_135_en <= 1'b0;
else
// Inhibit first and last pulses to prevent clocking out timing codes
clk_135_en <= (~sav & input_phase[0]
& ~(timing_ref & ((din == 8'h9d) | (din == 8'hda))));

reg [8:0] line;
always @(posedge clk or negedge reset_n)
if (~reset_n)
line <= 9'b0;
else if (v)
line <= 9'b0;
else if (timing_ref_r & sav)
line <= line + 9'b1;

reg [9:0] pixel;
always @(posedge clk or negedge reset_n)
if (~reset_n)
pixel <= 10'b0;
else if (h)
pixel <= 10'b0;
else if (clk_135_en)
pixel <= pixel + 10'b1;

endmodule // bt656_rx