SCI 2012 An Ultra-Low Power ECG Acquisition and Monitoring ASIC System for WBAN Applications

Abstract—

An Ultra-Low Power ECG Acquisition and Monitoring ASIC System for WBAN Applications Xin Liu,Yuanjin Zheng,Member,IEEE,Myint Wai Phyu,F.N.Endru,V.Navaneethan,and Bin Zhao

electrocardiogram(ECG)acquisition and signal processing ap-

plication sensor node for wireless body area networks(WBAN).

This sensor node can accurately record and detect the QRS peaks

of ECG waveform with high-frequency noise suppression.The

proposed system is implemented in0.18-m complementary

metal–oxide–semiconductor technology with two chips:analog

front end integrated circuit(IC)and digital application speci?c

integrated circuit(ASIC),where the analog IC consumes only

79.6W with area of4.25mm2and digital ASIC consumes9

W at32kHz with1.2mm2.Therefore,this ECG sensor node is

convenient for long-term monitoring of cardiovascular condition

of patients,and is very suitable for on-body WBAN applications.

Index Terms—Analog front end,digital application speci?c inte-

grated circuits(ASIC),electrocardiogram(ECG),QRS detection,

signal acquisition,wavelet transform.

I.I NTRODUCTION

R ECENTLY,the research on wireless body area network

(WBAN)applications develops rapidly and receives

more and more attentions,which various sensors are attached

on clothing or implanted in human body.Different biomedical

signals are acquired and processed jointly.The recorded vital

body parameters and the control commands are wirelessly

transmitted between sensor nodes and the base station such

as personal digital assistant(PDA)or laptop.The system is

further connected with a healthcare center for detailed analysis

and diagnosis by medical professionals.In Fig.1,a typical

application example of WBAN techniques are demonstrated.

Bene?ting from rapid technology advances in wireless commu-

nication,signal processing,biomedical sensing,and integrated

circuits,the WBAN technology is able to develop miniature,

lightweight,ultra-low power physiological healthcare surveil-

lance and monitoring devices,for the improvement of human

lives[1]–[6].

Manuscript received October03,2011;revised January10,2012and

February05,2012;accepted February06,2012.Date of publication March

14,2012;date of current version April11,2012.This work was supported

by the Science and Engineering Research Council of A*STAR(Agency for

Science,Technology and Research),Singapore(Program of Embedded and

Hybrid System Phase II(EHSII),SERC Grant0521180055).This paper was

recommended by Guest Editor H.-J.Yoo.

X.Liu,M.W.Phyu,F.N.Endru,V.Navaneethan,and B.Zhao are with the

Institute of Microelectronics,A*STAR,117685Singapore(e-mail:liux@ime.a-

https://www.360docs.net/doc/923357669.html,.sg).

Y.Zheng is with the Institute of Microelectronics,A*STAR,117685Singa-

pore and also with School of Electrical and Electronic Engineering,Nanyang

Technological University,639798Singapore(e-mail:yjzheng@https://www.360docs.net/doc/923357669.html,.sg).

Color versions of one or more of the?gures in this paper are available online

at https://www.360docs.net/doc/923357669.html,.

Digital Object Identi?er10.1109/JETCAS.2012.2187707

Fig.1.Demonstration of wireless body area network technique.

Electrocardiogram(ECG)is the most important indicator

among all the vital body parameters,for diagnosing many

cardiac diseases.ECG is the electrical representation of the

contractile activity of the heart over time,which can be easily

recorded using noninvasive electrodes on the chest or limbs.

ECG indicates the overall rhythm of the heart and weaknesses

in different parts of the heart muscle,and can measure and

diagnose abnormal rhythms of the heart[7].Therefore,there is

an increasing demand for long-term and real-time monitoring

and analysis of ECG signal for early diagnosis and improved

treatment of cardiac diseases.ECG can be represented by a

cyclic occurrence of patterns with different frequency contents

(QRS complex,P and T waves).In the ECG waveforms,QRS

complex re?ects the electrical activity within the heart during

the ventricular contraction.It provides much information about

the state of the heart[8].In this sense,detecting QRS peaks in

the ECG is one of the most important tasks that need to be per-

formed.This stage is crucial in basic ECG monitoring systems

and is important for all other ECG processing applications[9].

Nevertheless,monitoring ECG signal possesses some chal-

lenges as it is considered to be a weak signal.According to[10],

the signal amplitude can range from100to4mV.The main

bandwidth of ECG signals spans from0.1to250Hz,whereby

?icker noise is dominant.In addition,this signal is sus-

ceptible to common-mode interference from the mains supply

and the problem of offset generated by skin–electrode interface.

With this kind of condition,the analog front-end should be able

to provide enough noise rejection in order to be able to amplify

such signal.The gain and bandwidth of the front-end ampli?er

should be adjustable in order to deal with the different charac-

teristic of the signal.

For the purpose of ECG monitoring,various types of QRS

peak detection algorithms have been proposed,including

2156-3357/$31.00?2012IEEE

This paper proposes a power and area ef?cient

?lter-banks method[9],arti?cial neural networks[11],genetic algorithms[12],and geometrical matching approach[13].Most of such algorithms have comparatively high computational complexity and are not very suitable to be implemented in application speci?c integrated circuits(ASICs).The variety of QRS complex shape morphologies and artifacts causes the per-formance of QRS complex detection algorithms that use?xed bandwidth band-pass?lters and?xed width integration win-dows to decrease when the QRS morphology changes.To avoid this problem,a new approach to QRS complex detection based on wavelet transform(WT)has been introduced[14],[15]. Wavelet transform is a mathematical function that separates the signal into different frequency bands(scales)[16].It is a very promising technique for processing time-varying biomedical signals,such as ECG.The WT decomposes the ECG signal into several scales,where each scale has different bandwidth and time support.WT at any scale is done by?ltering the signal with an appropriate?lter.The most common approach to QRS complex detection is to?nd local maxima at four consecutive scales.In[17],the hidden Markov tree(HMT)model was used to characterize the point statistics of wavelet coef?cients across scales.For instant,if a wavelet coef?cient produced by a true signal is of large magnitude at a?ner scale,its parents at coarser scales are likely to be large as well.However,for those coef?cients caused by noise,the magnitudes will decay rapidly along the scales.With the observations from[17],[18] analyzed the multiscale products and applied them to step detection and estimation.[19]multiplied the adjacent wavelet scales to sharpen the important structures while weakening noise.[20]presented a new online detection algorithm based on a multiscale product sequence in wavelet domain to identify the rapidly changing points effectively.

In[21],we presented some digital ECG signal processing ap-plication speci?c integrated circuits(ASIC),which achieves low power consumption and high hardware ef?ciency.This paper only focuses on the digital system architecture and circuitry de-sign.In this extended paper,we propose a recon?gurable analog front-end and ADC,which interfaces with the digital signal pro-cessing module,so that a complete ECG acquisition and mon-itoring system is proposed and demonstrated for WBAN appli-cations with ultra-low power and small silicon area.Since the signal acquisition front-end is a recon?gurable design which can be applicable for other biomedical applications,a two-chip solution is proposed.In the signal acquisition ASIC,the gain and bandwidth of the front-end are adjustable and a low power sigma-delta ADC is used for signal digitalization.In the digital ECG signal processing ASIC,the real-time accurate QRS peak detection is realized based on wavelet transform with high fre-quency noise suppression.In more details,to acquire the ECG waveform and digitalization,our design includes a highly inte-grated analog ECG acquisition front-end,including a chopper-stabilized preampli?er,a variable gain ampli?er(VGA),and a third-order sigma-delta ADC with digital decimation?lter.In the digital ECG signal processing ASIC,to exploit the wavelet interscale dependencies,we multiply the adjacent wavelet sub-bands to enhance the edge structures while weakening noise. Thereafter,a threshold is calculated and imposed on the sum-mation of products,instead of on the wavelet coef?cients,

to Fig.2.Block diagram of the proposed ECG monitoring system

architecture.

Fig.3.Block diagram of the proposed digital signal processing ASIC for ECG. identify the important features.Therefore,our design achieves low error rate QRS peak detection.This chip enables the ECG signal processing at the sensor node with low area and power https://www.360docs.net/doc/923357669.html,bined with the wireless transceiver,the ECG QRS peak information can be extracted accurately and wire-lessly transmitted to the healthcare server for monitoring and diagnosis.Therefore,the proposed ECG ASIC is very suitable for battery-supplied healthcare WBAN applications.

II.A RCHITECTURE AND C IRCUIT D ESIGN

The proposed system architecture,which includes both analog ECG acquisition front-end and digital signal processing back-end,is shown in Fig.2.The analog front-end consists of chopper-stabilized preampli?er followed by variable gain ampli?er with adjustable gain and bandwidth.Fully-differential architecture is employed in order to suppress the common-mode noise and interferences on the signal.As the interface between the analog front-end and Digital ASIC processor,a third-order sigma-delta ADC with digital decimation?lter follows the front-end to convert the ampli?ed signal to digital format.The digitalized ECG signal is then fed into digital signal processing module to detect the QRS peaks as shown in Fig.3.To achieve satisfactory QRS peak detection performance,the digital signal processing block decomposes the digitalized ECG signal into different wavelet scales.The noise is suppressed?rstly using the multiscale wavelet analysis,and then QRS peaks are detected. The novelty of the design in the paper is that we introduce recon?gurability to the analog front-end system so that it can extend to handle different kinds of bio-potential signals by just using the same analog IC chip.In addition,a complete signal condition and analysis system including analog acquisition IC and digital ASIC processor are demonstrated.As indicated above,the proposed analog front-end IC is designed with recon?gurable function,which is achieved by making:1)input noise of the preampli?er is low enough(100

nV–1),suitable for acquisition of different kinds of bio-potential signals such as ECG/EEG/EMG/Neural signals etc.;2)total gain range (40–100dB)of preampli?er and VGA is across a large range to cover different dynamic range of bio-potential signals;3)the bandwidth of analog front-end is tunable(low pass corner100 Hz–2KHz);4)the clocking rate for sigma-delta ADC can be changed so that the EONB can be con?gured for different kind of signals.(e.g.,ECG8bit,EEG12bit).

Fig.4.Circuit schematic of chopper-stabilized preampli?er.

A.Chopper-Stabilized Preampli?er

The preampli?er is mainly used to provide a necessary ampli-?cation to the signal without introducing signi?cant noise from the devices.For this reason,chopper stabilization was selected

to primarily remove the

noise that might deteriorate the SNR at the intended low frequency application.Fig.4shows the circuit schematic of the preampli?er.

The preampli?er was designed based on negative feedback gm-boosted source degenerated differential pair with resistive loads [22].The topology in [22]was modi?ed by utilizing a CMFB to generate the desired common mode voltage at the am-pli?er output.The resistive load was replaced with MOS load transistor.The loading effect to set the respective gain is per-formed by placing a resistor with each node connected to each output of the ampli?er.Chopper stabilization is employed by placing a modulator before the input and a demodulator after the output of the ampli?er.

A fourth-order low-pass ?lter follows the ampli?er to remove noise and inherent dc offset of the ampli?er that has been modulated to the chopper frequency of 16kHz.The fourth-order low-pass ?lter consists of two OTA-based second-order low-pass ?lters in series.With a cutoff frequency of 2.57KHz,the fourth-order ?lter is suf?cient to provide attenuation of at least 60d

B at the chopper frequency.A simple ring oscillator was designed to provide an on-chip 16kHz chopper clock signal.A pair of external capacitors (for ac coupling)is used before preampli?er to remove dc offset,which is to facilitate the fast prototype of the complete system.The CMRR of the overall system is therefore limited due to the nonperfect matching of ex-ternal capacitors.Furthermore,the power-noise ef?cient pream-pli?er design by Yazicioglu [23]can potentially be incorporated into our future design.B.Variable Gain Ampli?er

The variable gain ampli?er is used to further amplify the signal,while providing ?exibility in setting the ampli?cation factor and pass-band bandwidth.Fig.5shows the system struc-ture of the VGA.It has 3-bit gain control and 4-bit bandwidth control.

The structure of the VGA can be divided into two stages.The ?rst stage is an OTA with source degenerated differential pair.This stage performs gain control by tuning the value of

Fig.5.System structure of VGA.

source degeneration resistor of the differential input pair.The second stage is a pass-band block that provides further tuning of the gain and control of the bandwidth.This stage comprises of gain-BW control block,followed by an OTA.The gain tuning is done through gain-BW control block by changing the value of capacitor on its output.This capacitor,together with capacitor ,forms capacitive divider.The bandwidth control is done by tuning the value of capacitor at the input of this block.This capacitor acts as a load for the OTA on the ?rst stage.

The VGA was designed to have gain range from 8to 58dB.The high-pass corner was set at 0.015Hz and the low-pass corner is tunable from 100Hz to 2kHz.C.Sigma–Delta ADC

In this design,sigma–delta modulator is employed together with digital decimation ?lter.Single-loop 1-bit sigma-delta ADC was particularly selected due to its simplicity and insensitivity to imperfections of analog circuits [24],[25].Prior to its implemen-tation,system level simulations in MATLAB were performed in order to derive the modulator requirements and speci?cations for individual sub-blocks.Fig.6shows the MATLAB system level model of the modulator with cascaded integrator feedback archi-tecture.In most of ECG/EEG signal acquisition applications,the requirement of ENOB of ADC is at least 8bits.Based on the sim-ulation,it can be found that third order meets this requirements and with good signal shaping capability.

The system diagram of sigma–delta ADC is shown in Fig.7.Fig.7(a)shows the equivalent switched capacitor realization of Fig.6.Fully-differential current mirror OTA is used in order to accommodate the low supply voltage and to provide more power ef?ciency.To implement the switch,bootstrapped switch

Fig.6.MATLAB system block diagram of

ADC.

Fig.7.System diagram of sigma–delta ADC:(a)switched capacitor realization of modulator;(b)block diagram of decimation ?lter.

reported in [26]is adopted.This switch was designed to operate at low voltage with device reliability considerations.The single bit quantizer is realized with a dynamic comparator followed by an SR latch.The comparator is a purely dynamic circuit,which consumes low power [27].The modulator was designed to achieve 50–60dB SNR and SFDR of 50dB over a bandwidth of 500Hz.The switching clock is derived from an on chip clock generator which gives choice on over sampling ratio of 32.Following the ADC,a decimation ?lter with decimation factor of 32is used as shown in Fig.7(b).The ?lter consists of one cascaded integrator-comb (CIC)?lter and two stages of half-band ?lters (HBF).The decimation ?lter is used in order to reduce the sampling rate of the ADC output and to suppress the out-of-band noise.

D.Four-Scale Wavelet Decomposition

The digitalized ECG waveform from decimator ?lter is fed into the digital ECG signal processing module.For ECG moni-toring purpose,the QRS peaks of ECG need to be detected.The received ECG signal is normally corrupted by many types of noise and interference,such as circuit noise and other biomed-ical signals.If we directly detect the QRS peak using the original recorded ECG waveforms,it may downgrade the detection per-formance due to noise.In order to effectively enhance the QRS

detection performance,an appropriate signal processing proce-dure for noise reduction is necessary before QRS detection.In general,the QRS detection algorithm is divided into a pre-processing stage or feature extraction stage including linear or nonlinear ?ltering and a decision stage including peak detec-tion and decision logic [28],[29].In our design,we perform a discrete wavelet transform with four-scale decomposition on the

recorded noisy ECG

signal

to extract the ECG features and characteristic points.The input ECG signal is sampled at 1kHz sampling rate for high resolution ECG analysis.Two types of ?nite impulse response (FIR)?lters are deployed in each scale,i.e.,high-pass ?lter (HPF)and low-pass ?lter (LPF).The out-puts of these ?lters can be down-sampled for removing the re-dundancy of the signal representation.However,the down-sam-pling procedure involves time-shifting issue for the signal rep-resentation,and reduces the temporal resolution of the wavelet coef?cients for when scales increase [30].Therefore,to avoid the issues of time-shifting and resolution degradation,we apply the same sampling rate in all scales.For

scale ,the outputs of decomposition

LPF and decomposition

HPF are given by

[10]

(1)(2)

where

and are the coef?cients of LPF and HPF of

scale ,respectively.For scale

1,

and are given by,respectively

[14]

(3)(4)

For

scale

,

and are obtained by

inserting zeros between each of the nonzero coef?cients

of

and [14],which can be implemented by shift registers.The LPF and HPF outputs of the input signal at

scale are equal to ?ltered signals of the input signal that passed through the equivalent

digital

?lters

and ,as given

by

(5)(6)

where represents the operation of convolution.Given 1kHz

input signal sampling rate,the 3dB bandwidths of the equivalent

?lter for

scales is provided in Table I.Since the QRS signal locates in low-frequency range [3Hz,40Hz].Therefore,four-scale WT is enough to extract the necessary characteristic points [31].If using higher scale WT,the computational complexity and power consumption will be greatly increased.

In Fig.8,the block diagram of four-scale DWT is illustrated.Since the coef?cients are symmetric,the number of multipliers can therefore be reduced into half.The data input to LPFs and HPFsare the sameat eachscale,the numberofdelay elements can therefore be shared to minimize the hardware cost.The numbers of nonzero coef?cients remain the same at different scales,and