laker介绍

Overview

Laker?

L3 is the only available Schematic-Driven Layout solution that provides full hierarchical manipulation capability to increase handcrafted layout productivity by a minimum of 2X. Using an intuitive methodology that includes schematic, constraints, and design rule driven layout, Laker L3 enables layout engineers to achieve correct-by-construction results. Most cutting edge foundries - including Chartered, Dongbu-Anam, GSMC, SMIC, TSMC, and UMC - offer foundry-certified Laker technology files ranging from 0.5um to 65nm for analog, mixed-signal, logic, memory, and RF processes.

Major Benefits

? Cuts layout time in half while sustaining important aspects of handcrafted layout density

? Total system allows user to create layout from floor planning, device creation, placement, wire connection, to layout

verification and correction without the need for data translation ? Supports latest process design rules to meet the physical

implementation requirements of Ultra-Deep-Submicron (UDSM) and Design-For-Manufacturing (DFM)

? Fully customizable bind keys to increase individual productivity and reduce the learning curve for new users

? Device-level manipulation reduces tedious/error-prone layout creation and editing.

? Shape and Grid Based routers for both full custom and cell-based design applications

? Download foundry-certified Laker technology files to instantly use the "plug-and-play" Laker solution

? Schematic-Driven Layout Flow works efficiently with legacy and new designs

Major Features

Integration Capability

? Versatile System: Import designs from EDIF, Spice netlist, or work with Laker-AMS to perform Schematic-Driven Layout flow.? Integration with 3rd party physical verification solutions: Tight link with Mentor Graphics Calibre? and Synopsys

Hercules? for DRC/LVS. Run Calibre? or Hercules on one block or the whole chip directly from the Laker menu.

Layout Planning

? Custom Floor Planner: Supports block area estimation with reshaped aspect ratio. Assigns pin locations automatically and provides congestion map information to offer best-practice floor planning scheme. Mixes Soft and Hard Instances to minimize the gap between top-down planning and bottom-up layout realization.

? Stick Diagram Compiler: Provides a higher level of abstraction enabling more efficient transistor floorplanning, such as gate merging, swapping and splitting.

? Automatic Transistor Placer: Optimum transistor placement achieved automatically through chaining, folding, and connectivity-based placement.

? Matching Creator: Customize transistor symmetry using a high level abstraction matching table. Quickly realize transistor placement according to user-defined matching patterns.

Advanced Device Model

? Magic Cell? (MCell): Built-in UDSM DRC-correct device generator. Provides flexible device models thus enabling

extremely efficient creation of the devices physical layout from circuit components of a netlist or schematic. Magic Cell? reduces the effort for device preparation and provides higher levels of device manipulation. Most importantly, Magic Cell? is the only device model that has the ability to deliver handcrafted quality and guarantee zero DRC violations.

Built-in Shape and Grid Based Router

? Net Router: Automatically route single or multiple nets, DRC and LVS clean.

? Point to Point Router: Click on source and target to

automatically create a DRC clean route. Or use it in an interactive mode while routing between source and target. Interactive settings for each layer include (1) availability for routing, (2) horizontal and vertical cost functions, and (3) width and space.? Pathfinder: Interactive single layer DRC-correct path creator. Router "follows the mouse" in a point and click mode,

recognizing same layers and routing around them. Use bind keys to switch between routing layers.

? Route by Label: Using text, or labels, as a guide, routes are automatically created between multiple points.

Hierarchy Manipulation Capability

? Manipulate circuit hierarchy on Design Browser or Layout Window in order to optimize layout.

Pattern Recognition Technology

? Copy & Associate: Automatically comb through design database to find matches for selected items. Then automatically copy physical layouts and assign correct connectivity. Drastically reduce time spent on building repeat circuitry.

? Pattern Reuse: Automatically comb through design database to find matches for cells where the hierarchy of the physical layout does not match that of the original schematic. Copy patterns and create new layouts with correct connectivity. Drastically reduce time spent on building repeat circuitry.

Correct-by-Construction

? Rule-Driven Editing: While editing polygons, automatically check, display, and snap to width, space, notch, overlap, and enclosure rules. Increases productivity by reducing need to use rulers and "look up" design rules.

? Flight Lines & Real-Time Short Detector: Flight Lines guide user on where to wire. Real-Time short detector displays short errors as they are created. Both are used to ensure LVS-correct layout results.

? Push Wire: Create a path where you want, push-wire will move same layer routes out of the way.

ECO Capability

? Laker compares an ECO netlist with the existing layout and then displays physical and/or logical discrepancies in the Design Browser window. Use automated functions to fix the

discrepancies and match the layout back to the schematic.

Layout Debugging and Correction

? Auto DRC Correction: Fix DRC violations automatically, based on user selected area or Laker DRC error viewer. All fixed layout results will keep original connections, so as not to introduce additional LVS violations. Supports Laker-iDRC, Calibre, and Hercules DRC verification tool error reports.

? Hierarchical Net Tracer: Provides a unique feature to trace physical net connectivity through any/all levels of hierarchy.? Verification Explorer: Seamless integration with third-party industry standard layout verification tools allows the user to browse and debug DRC errors.

Cut Layout Time in Half

L3 DATASHEET

M0 N1 I1 VSS N W=WN1 L=LN1M1 N1 I2 N2 N W=WN2 L=LN2

Custom Floor Planner with Soft Instance

After auto pin assignment

Stick Diagram Complier

A Stick Diagram Complier brings transistor planning to a higher level of abstraction. The layout designer can manipulate the transistors at the symbolic level. All wire connections and their corresponding net names are shown in the Stick Diagram Complier. Different nets can be highlighted with different colors to help routing analysis. The Stick Diagram Compiler makes transistor planning much easier when compared with a conventional full custom flow.Features include:

? Allows layout designer to swap, merge, move spilt and align gate at symbolic view.

? The built-in "greedy" router instantly displays the estimated requirement for routing tracks based on the current transistor placement.

? A layout preview can be turned on to show the actual layout of devices before realizing these transistors into the layout window.

Automatic Transistor Placer

Laker provides a multi-row placement capability for PMOS and NMOS transistors. The transistor placer will display the best transistor placement for area and routing based on given placement criteria, such as maximizing diffusion sharing, minimizing the routing tracks, and maximizing poly gate alignment.

Features include:

? Cell Template constraint settings include P/N MOS space, strip height, P/N MOS alignment mode, power layer, power rail width, and maximum folding width to name a few.

? Automated transistor chaining, folding and placement is achieved according to user defined Cell Template constraints.

? The resulting placement can be displayed in a Stick

Diagram Compiler for further optimization by using features such as gate swapping, moving, aligning, splitting, merging and folding.

Matching Creator

The user can select a default matching pattern or define new matching pattern(s) in the Patterns Table. Based on a given matching pattern, Laker will provide an efficient placement scheme to match transistors or instances.

Cell Template for placement constrains

Stick Diagram displays the placement result and assists in the transistor planning process

Finish matching placement in minutes

Automated Devices Generator

Magic Cell? (MCell)

Laker uses an innovative approach to overcome traditional device generator restrictions. Laker fully supports Ultra-Deep-Submicron DRC and DFM rules using process rules built into the technology file, and quickly generates DRC-correct layouts without additional programming. MCell? devices can be further edited using manual methods allowing the designer to achieve any level of handcrafted quality. Most importantly; MCell? guarantees a DRC-correct layout when the editing is complete.

Features include:

? Supports multiple-gate transistors, guard-rings, contact

arrays, inter-digitized resistors and capacitors with optimized layout structures.

? Provides DRC-correct device construction and higher device-level manipulation such as merge, split, insert, subduce, fold, align, link and optimize.

? Typical polygon-push editing commands like stretch, chop and reshape can be applied to the MCell? as well.

? Geometry compaction technology is available to ensure optimized layout structures and DRC-Correct results.

Rule-Driven Editing

Rule-Driven Editing checks the relevant design rules and notifies the user of violations in real-time. With Rule-Driven editing, Laker enables a true correct-by-construction result, greatly reducing verification and debug iterations.

Features include:

? Concurrent display of all necessary rule distances while editing.

? Automatically snaps the cursor to the minimum design rule.

? Supports Ultra-Deep-Submicron DRC rules.

Merge Gate

Before After

Before After

Before

After

Before

After

Split Gate

Insert Gate

Subduce Gate

Rule-Driven Editing provides DRC violation alerts and distance display in real-time

Support stack via Easy reshape & chop

Inter-digitized resistors and capacitors

Add dummy gates to transistor automatically

Corporate Headquarters 2870 Zanker Road, Suite 210

San Jose, CA 95134

Tel: +1 408-321-0888

Fax: +1 408-321-0880

info@https://www.360docs.net/doc/e74890572.html,

Japan

Novaflow, Inc.

Tel: 81-45-4708890

Fax: 81-45-4708891Asia Headquarters

3F No. 25, Industry East Rd. IV,

Science-Based Industrial Park,

Hsinchu 300, Taiwan R.O.C.

Tel: +886 3-5794699

Fax: +886 3-5794899

sales@https://www.360docs.net/doc/e74890572.html,

Korea

KT Design Technology Co., Ltd

Tel: 82-2-2140-5500

Fax: 82-2-2140-5555

China / Hong Kong

Sprignsoft Co., Ltd (Shanghai)

Tel: 86-21-5490-2090

Fax: 86-21-5490-2093

Singapore / Malaysia

Waiz Pte Ltd.

Tel: 65-6451-5217

Fax: 65-6451-5217

India

CMR Design Automation P. Ltd.

Bangalore

Tel: 91-80-2527-6866

Fax: 91-80-2527-9741

Delhi

Tel: 91-11-4163-7128

Fax: 91-11-5163-7853

Built-in Shape and Grid Based Router

Upon completion of device placement, the layout designer can use the built-in Shape and Grid Based Router, together with retained connectivity to finish wiring "on the fly".

DRC Correction

Auto DRC Correction

Repairing DRC violations is a very tedious task. Laker provides a powerful automatic DRC fixing function that repairs DRC violations in seconds.

Features include:

? Spacing, width and enclosure rules

? Supports Calibre, Hercules and other industry standard verification tools.

? Automated correction scheme includes a DRC error flag viewer that allows the user to select & repair targets one-by-one, or by a specifying a target area. Open System

Complete TCL/TK Support

Laker supports complete TCL/TK language syntax plus some extensions for maximum flexibility in tool customization, database query, and layout creation.

Supported Platforms

Laker supports many popular hardware platforms, including major UNIX workstations running Sun Solaris, HP-UX, and PC Linux.

SUN Solaris SunOS 5.5, 5.6 (32-bit) or 5.7 (64-bit)

HP HP-UX 10.X (32-bit) or HP-UX 11.X (64-bit)

PC Linux Redhat 7.2, 8.0 and 9.0 or AMD64

Next Generation Custom Layout Automation System

Over 2,000 chips have been taped out utilizing Laker. More than 200 companies including, cutting edge IDMs, pure-play foundries, and fabless semiconductor companies have changed to Laker for their custom layout flow. Laker's fast growing market share is the best proof of its ability to help customers better compete in their respective markets.

Laker makes business sense.

Before Auto DRC fixing

After Auto DRC fixing

Before net routing

After net routing