单片机外文翻译

外文文献：

Double switched reluctance motors parallel drive based on dual

89C52 single chip microprocessors

Abstract

The developed double Switched Reluctance motors parallel drive is presented, which is made up of two four-phase 8/6 structure Switched Reluctance motors, two four-phase asymmetric bridge power converters and the controller. The four-phase 8/6 structure Switched Reluctance motor, the four-phase asymmetric bridge power converter and the control scheme are described. The closed-loop rotor speed control of the main motor and the closed-loop rotor speed control of the subroutine motor could be based on the pulse width modulation fuzzy logic algorithm, which is implemented by dual 89C52 single chip microprocessor controller. The experimental results of rotor speeds and phase currents in two Switched Reluctance motors are given.

Keywords: switched reluctance; fuzzy logic; microprocessor

1.Introduction

The electric locomotives in coal mines are driven by series direct current motor drive system. The accessional resistor regulated control or the chopping control is used to adjust the rotor speed of the series direct current motor and to control the speed of electric locomotive.

The Switched Reluctance motor drive can be operated at four quadrants[1]. It could be used as electrical traction for electric locomotives in coal mines[2][3]. The soft mechanical characteristics of Switched Reluctance motor drive[4] contribute to parallel double Switched Reluctance motor drives system with synchronization of the rotor speed and the loads being in equilibrium. The double Switched Reluctance motors parallel drive system can be used to replace the series direct current motor drive system as the adjustable speed motor drive for the electric locomotives. The Switched Reluctance motor drive is made up of the Switched Reluctance motor, the power converter and the digital controller. There are four-phase 8/6 structure Switched Reluctance motor and three-phase 6/4 structure Switched Reluctance motor. The fault tolerance ability of four-phase 8/6 structure Switched Reluctance motor is higher than that of three-phase 6/4 structure Switched Reluctance motor so that four-phase 8/6 structure Switched Reluctance motor is adopted in the system. There are asymmetric

bridge circuit, bifilar winding circuit, common switch circuit, resistance commutation circuit, split supply circuit, inductance commutation circuit for four-phase power converter with four-phase 8/6 structure Switched Reluctance motor. The four-phase asymmetric bridge power converter circuit is adopted in the system due to its independence in each phase. The digital microprocessor has the advantages in high reliability and stability for control of Switched Reluctance motor drive. Some control algorithms can be implemented by the digital microprocessor. The Switched Reluctance motor drive is based on Intel 8031[5], Intel 80C196KB[6], Intel 87C196KC[7]. The 89C52 digital microprocessor had been developed for sliding mode and PI control of a single Switched Reluctance motor drive[8]. The paper presents dual 89C52 single chip microprocessors controller for double Switched Reluctance motors parallel drive. It is not easy to gain the exact mathematical model of Switched Reluctance motor drive since it has nonlinear magnetic paths in the motor and nonlinear circuit topology in the power converter. It is not necessary for the fuzzy logic control to gain the exact mathematical model of Switched Reluctance motor drive. The rotor speed closed-loop control could be implemented based on the fuzzy logic algorithm.

2.Scheme of system

The developed double Switched Reluctance motors parallel drive consists of two four-phase 8/6 structure Switched Reluctance motors, two four-phase asymmetric bridge power converters and the digital controller.

1.1.Motor

Two four-phase 8/6 structure Switched Reluctance motors are adopted in the developed double Switched Reluctance motors parallel drive. The cross section of the four-phase 8/6 structure Switched Reluctance is shown in Fig.1. There are eight poles in the stator, while six poles in the rotor. The two coils on the diametrically opposite stator poles can be connected to make up a phase winding. There is only phase winding in the stator. There is no winding, no magnet and no brush in the rotor. There is a rotor position detector on the motor for detecting rotor position and speed. The photograph of the developed dual four-phase 8/6 structure Switched Reluctance motors is shown in Fig. 2.

Fig 1.Cross section of the four-phase 8/6 structure SR motor

Fig 2.Photograph of the developed dual four-phase 8/6 structure SR motors

2.2. Power converters

The main circuit of the two four-phase asymmetric bridge power converters with phase windings, “A1”, “B1”,“C1” and “D1”, “A2”, “B2”, “C2” and “D2”, is shown in Fig.3.

2.3. Control scheme

The turned-on angle and the turned-off angle of the main switches are fixed. The triggered signals of the main switches in the dual power converters are modulated by PWM signal. The closed-loop rotor speed control in the main Switched Reluctance motor could be implemented by comparison of the given rotor speed and the real rotor speed of main motor, and by regulation of the duty ratio of PWM signal in main power converter with fuzzy logic control algorithm. The closed-loop rotor speed control in the subroutine Switched Reluctance motor could be implemented by comparison of the real rotor speed of main motor and the real rotor speed of subroutine motor, and by regulation of the duty ratio of PWM signal in subroutine power converter with fuzzy logic control algorithm. The fuzzy logic control algorithm in an 89C52 digital microprocessor for the main motor could be

11i g f e n n =- (1)

where, the given rotor speed is g n , and the real rotor speed is 1f n , the deviation of the

rotor speed of the main motor at the moment of t i is 1i e . Variation from the deviation of the rotor

speed is as

()1111i i i e e e --=& (2)

where, e (i-1)1 is the deviation of the rotor speed at the moment of t i-1. The duty ratio of the PWM signal of the main motor at the moment of t i is

1(1)11i i i D D D -=+ (3)

where, 1i D is the increment of the duty ratio of the PWM signal at the moment of t i and (1)1i D - is the duty ratio of the PWM signal at the moment of t i-1. The fuzzy logic algorithm could be expressed as

if 11i

E E =%% and 11j EC EC =%% then 11ij U U =%%, i = 1,2,…, m, j = 1,2, …,n (4) where, 1

E % is the fuzzy set of the deviation of the rotor speed,1EC % is the fuzzy set of the variation from the deviation of the rotor speed, and 1

U % is the fuzzy set of the increment of the duty ratio of the pulse width modulation signal.

The fuzzy logic control algorithm in the other 89C52 digital microprocessor for the

subroutine motor could be as follows

212i f f e n n =- (5)

where, the real rotor speed of the subroutine motor is n f2, the deviation of the rotor speed of the subroutine motor at the moment of ti is e i2. The variation from the deviation of the rotor speed is as follows

1(1)1i i i e e e -=-& (6) where, e (i-1)2 is the deviation of the rotor speed at the moment of t i-1. The duty ratio of the PWM signal of the main motor at the moment of t i is

2(1)22i i i D D D -=+V （7）

where, 2i D V is the increment of the duty ratio of the PWM signal at the moment of t i and (1)2i D -is the duty ratio of the PWM signal at the moment of t i-1. The fuzzy logic algorithm could

be expressed as follows

if =%%22

i E E and =%%22j EC EC then =%%22ij U U , i = 1,2,…, m, j = 1,2, …,n (8) where, 2E %is the fuzzy set of the deviation of the rotor speed, 2

EC %is the fuzzy set of the variation from the deviation of the rotor speed, and 2

U %is the fuzzy set of the increment of the duty ratio of the pulse width modulation signal.

The closed-loop rotor speed control of the main motor and the closed-loop rotor speed control of the subroutine motor could be based on the pulse width modulation fuzzy logic algorithm, which is implemented by dual 89C52 single chip microprocessors controller. The photograph of the developed dual 89C52 single chip microprocessors controller is shown in Fig. 4.

The schematic diagram of the developed dual Switched Reluctance motors parallel drive prototype is shown in Fig.5. There are the protection circuit, the commutation circuit and the gate driver circuit in each motor drive system, respectively.

3.Experimental tests

The developed dual Switched Reluctance motors parallel drive prototype is supplied by DC 132V storage batteries. The experimental results in the rotor speed curves of the two motors are shown in Fig. 6. In Fig. 6 a) the given rotor speed n g = 400 r/min, b) the given rotor speed n g = 750 r/min, c) the given rotor speed n g = 1100 r/min. The experimental results in the phase current waveforms of the two motors are shown in Fig. 7. In Fig. 7 a) the given rotor speed n g = 400 r/min, b) the given rotor speed ng = 800 r/min, c) the given rotor speed n g = 1040 r/min. It is shown that synchronization of the rotor speeds of the motors is well. The difference in the peak value of phase current of the two motors and in phase current waveforms of the two motors is small. It means that the loads are distributed on the two motors in equilibrium.

Fig. 3. Main circuit of the power converters Fig. 4. Photograph of the developed digital controller

Fig. 5. Schematic diagram of the developed dual Switched Reluctance motors parallel drive prototype

4.Conclusions

The soft mechanical characteristics of Switched Reluctance motor drive contribute to parallel dual Switched Reluctance motors with synchronization of the rotor speed and the loads being in equilibrium. The prototype made up of two four-phase 8/6 structure Switched Reluctance motors, two four-phase asymmetric bridge power converters and the digital controller is developed. The closed-loop rotor speed control in the main Switched Reluctance motor and the closed-loop rotor speed control in the subroutine Switched Reluctance motor are implemented by PWM fuzzy logic control algorithm, which are based on dual 89C52 digital microprocessors. The experimental results in the rotor speed curves of the two motors and in the phase current waveforms of the two motors show that synchronization of the rotor speeds of the motors is well and the loads are distributed on the two motors in equilibrium.

a)b) c)

Scale: Abscissa: 0.5 s/div., Ordinate: 500 r/min/div.

Fig. 6. Tested rotor speed curves

a) Scale: Abscissa: 5.0 ms/div. b) Scale: Abscissa: 2.0 ms/div. c) Scale: Abscissa: 2.0 ms/div.

Scale: Ordinate: 4.0 A/div.

Fig. 7. Simulated phase current waveforms

Acknowledgements

The authors would like to thank the Project 20070290504 supported by Specialized Research Fund for the Doctoral Program of Higher Education of China.

References

[1] H Chen, G Xie. The parallel drive system of the double switched reluctance motors for locomotive traction application. Proceedings of the 27 Annual Conference of the IEEE Industrial Electronics Society, 2 (2001) 1483-1487.

[2] P. Greenhough, Switched Reluctance Variable Speed Drives-A Focus on Applications. Mining Technology, 4 (1996) 107-110.

[3] H. Chen and G. Xie, 80C31 Single Chip Computer Control of the Switched Reluctance Motor for Locomotive in Coal Mines. Proceedings

of 5th International Conference on Electrical Machines and Systems, I. (2001) 604-607.

[4] H Chen, D Zhang and G Xie. Study of the mechanical properties for the switched reluctance motor drive. Journal of China University of Mining & Technology, 5 (2001) 458-462.

[5] H Chen. Single chip microprocessor control for switched reluctance motor drive. KIEE International Transactions on EMECS, 4 (2002) 207-213.

[6] H Chen, W Cheng, G Xie, C Zhang. PID control of a switched reluctance motor drive with intel

80c196kb microcomputer. Proceedings of IEEE Hong Kong Symposium on Robotics and Control, 1 (1999) 304-307.

[7] H Chen and T Su. Control of The Switched Reluctance Motor Drive at Four Quadrants Based on Intel 87C196KC Single Chip Microprocessor. Dynamics of Continuous, Discrete and Impulsive Systems, Series B

(2005) 306-311.

[8] H Chen and X Zan. Sliding mode and PI control of switched reluctance motor drive. Dynamics of Continuous, Discrete and Impulsive Systems, Series B (2006) 427-431.

中文译文：

基于双89C52单片机微处理器双开关磁阻电动机并联驱动

摘要

开发的双开关磁阻电动机并联驱动的提出，它是由两个四相8/6结构的开关磁阻电机，两个四相非对称桥式功率转换器和控制器构成。四相8/6结构的开关磁阻电机，四相非对称桥式功率变换器和控制方案进行了描述。主电机和子程序马达的闭环转子速度控制的闭环转子速度控制，可以基于脉冲宽度调制模糊逻辑的算法，这是通过双重89C52单芯片微处理机控制器实现。给出转子的速度和两个开关磁阻电机的相电流的试验结果。

关键词：开关磁阻;模糊逻辑;微处理器

1.简介

煤矿里的电力机车是由一系列直流电动机驱动系统驱动的。附加的电阻调节器或斩波控制被用来调整串联直流电动机的转子速度，并控制电力机车的速度。开关磁阻电机驱动器可以在四象限运行[1]。它可以被用作电牵引电力机车在煤矿[2][3]。开关磁阻电机驱动的软机械特性[4]有助于平行双开关磁阻电机驱动系统与转子转速同步和负载平衡。

双开关磁阻电动机并联驱动系统可用于替代系列直流电动机驱动系统的可调速电动机驱动的电力机车。开关磁阻电机驱动由开关磁阻电机，功率变换器和数字控制器组成。

包括四相8/6结构开关磁阻电机和三相6/4结构开关磁阻电机。四相8/6结构开关磁阻电机的容错能力比三相6/4结构开关磁阻电机的高，因此采用四相8/6结构开关磁阻电机系统。有不对称的桥电路，双线绕组电路，常见的开关电路，电阻整流电路，分立电源电路，四相电源转换器，四相8/6结构开关磁阻电机电感整流电路。由于四相非对称桥式功率变换器电路在在系统中其各相独立通过，因此该数字微处理器具有高可靠性和稳定性开关磁阻电机驱动控制的优势，一些控制算法可以由数字微处理器来实现。开关磁阻电机驱动是基于英特尔8031[5]，英特尔80C196KB[6]，英特尔87C196KC[7]的系统。89C52数字微处理器已经制定了滑动单开关磁阻电机驱动的模式和PI控制[8]。本文介绍了双89C52单片机微处理器控制器，双开关磁阻电动机并联驱动。获得开关磁阻电机驱动的精确数学模型很难，因为它具有在功率变换器的电机和非线性电路拓扑非线性磁路。对于模糊逻辑控制没有必要获得开关磁阻电机驱动的精确数学模型。转子速度的闭环控制可以基于模糊逻辑的算法来实现。

2.系统方案

所开发的双开关磁阻电动机并联驱动由两个四相8/6结构开关磁阻电机，双四相不对称桥功率转换器和数字控制器构成。

2.1电机

两个四相8/6结构开关磁阻电机采用双开关磁阻电动机并联驱动。四相8/6结构的开关磁阻的横截面示于图1。有八个磁极的定子，而六个极中的转子。在径向相对的定子磁极上的两个线圈可以连接到构成一个相绕组。在转子里没有缠绕，没有磁铁，也没有刷，仅存在相绕组的定子。有一个转子位置检测器用于检测电动机转子的位置和速度。在开发的双四相8/6结构的开关磁阻电机的照片示于图2。

图 3. 四相8/6结构的SR电机的横截面

图 4. 在开发的双四相8/6结构SR电机的照片

2.2电源转换器

两个四相非对称桥式功率变换器的相绕组的主电路:“A1”，“B1”，“C”和“D1”，“A2”，“B2”，“C2”和“D2”，是图3所示。

2.3控制方案

导通的角度和主开关的关断角是固定的。在双电源转换器的主开关的触发信号由PWM 信号进行调制的。在主开关磁阻电机的闭环转子速度控制可以由给定的转子速度和主电机的实际转子速度的比较来实现，并且通过PWM信号在主功率变换器以模糊逻辑控制占空比

调节的算法实现。在子程序的开关磁阻电机的闭环转子速度控制可通过主马达及子程序电动机的实际转子速度的实际转子速度的比较来实现，并且通过PWM 信号的子程序功率变换器占空比调节模糊逻辑控制算法。在一个89C52数字微处理器的模糊逻辑控制算法，主电机可以是

11i g f e n n =- (1)

式中，给定的转子速度是g n ，真正的转子速度是1f n ，主电机的转子速度中的t i 的时刻1i e 的偏差。从转子速度的偏差的变化是

()1111i i i e e e --=& (2)

式中，e (i-1)1为转子速度中的t i-1的时刻的偏差。主电机的PWM 信号的t i 的时刻的占空

比为：

1(1)11i i i D D D -=+ (3)

式中，1i D 是在PWM 信号中的t i 的时刻增加的占空比，(1)1i D -是所述PWM 信号中的t i-1的时刻的占空比。模糊逻辑算法可以表示为

如果 11i

E E =%%且11j EC EC =%% 则 11ij U U =%%, i = 1,2,…, m, j = 1,2, …,n (4) 式中，1E %是模糊集的转子速度的偏差的，1

EC %是模糊集合从转子转速的偏差的变化，和1

U %是模糊集合的脉冲宽度调制信号的占空比的增量。在其它89C52数字微处理器电机子程序的模糊逻辑控制算法的可以是如下

212i f f e n n =- (5)

式中，电机子程序的实际的转子速度是2f n ，子程序电动机的转子速度中的t i 的时刻的

偏差是2i e 。转子转速的偏差如下：

1(1)1i i i e e e -=-& (6) 式中，e (i-1)2是转子速度中的t i-1的时刻的偏差。主电机的PWM 信号的t i 的时刻的占空

比

2(1)22i i i D D D -=+V （7）

式中，2i D V 是在PWM 信号中的TI 的时刻的占空比的增加，而(1)2i D -是所述PWM 信号中

的t i-1时刻的占空比。模糊逻辑算法可表示如下

如果 =%%22

i E E 且 =%%22j EC EC 则 =%%22ij U U , i = 1,2,…, m, j = 1,2, …,n (8) 式中，2E %是模糊集的转子速度的偏差的，2

EC %是模糊集合从转子转速的偏差的变化，和2

U %是模糊集合的脉冲宽度调制信号的占空比的增量。主电机和子程序电机的闭环转子速度控制的闭环转子速度控制，可以基于脉冲宽度调制模糊逻辑的算法，这是通过双重89C52单芯片微处理器控制器实现。发达双89C52单芯片微处理器控制器的照片示于图4。

在开发的双开关磁阻电动机并联驱动原型的示意图示于图5。各电动机驱动系统都分别有保护电路，换向电路和栅驱动电路。

3.实验测试

所开发的双开关磁阻电动机并联驱动的原型是由直流132V 蓄电池供电。在两个电动机的转子速度曲线的实验结果示于图6。图6 a ）在给定的转子速度n g = 400转/分钟，b ）该给定的转子速度n g = 750转/分，c ）该给定的转子速度n g =1100转/分。它表示电机转子的速度同步很好。在两个马达的相电流的峰值和在相位两个电动机的电流波形的差异是很小的。这意味着负载分布在处于平衡状态的两个电机上。

图 3. 电力转换器的主电路图 4. 在开发的数字控制器的图片

图 5. 在开发的双开关磁阻电动机并联驱动的原型示意图

4.结论

开关磁阻电机驱动的软机械特性有助于平行双开关磁阻电机转子速度同步和负载平衡之中。这个被开发的系统由两个四相8/6结构的开关磁阻电机，两个四相非对称桥式电源转换器和数字控制器组成。在主开关磁阻电机以及在子程序开关磁阻电机的闭环转子速度控制的闭环转子速度控制由PWM模糊逻辑控制算法，这是基于双89C52数字微处理器实现的。在两个电动机的，并在两个电机的相电流的波形，转子速度曲线的实验结果表明，该转子转速的电机的同步的载荷分布在处于平衡状态的两个电机。

b)b) c)

刻度：横坐标：0.5秒/格，纵坐标：500转/分/ DIV

图6.测试转速曲线

a）刻度：横坐标：5.0 ms /格b）刻度：横坐标：2.0 ms /格c）刻度：横坐标：2.0 ms /格。

刻度：纵坐标：4.0 A / DIV。

图 7.模拟相电流波形

致谢

笔者感谢了专项科研基金中国高等教育的博士计划支持的项目20070290504。

参考文献：

[2] P. Greenhough, Switched Reluctance Variable Speed Drives-A Focus on Applications. Mining Technology, 4 (1996) 107-110.

[3] H. Chen and G. Xie, 80C31 Single Chip Computer Control of the Switched Reluctance Motor for Locomotive in Coal Mines. Proceedings

of 5th International Conference on Electrical Machines and Systems, I. (2001) 604-607.

[4] H Chen, D Zhang and G Xie. Study of the mechanical properties for the switched reluctance motor drive. Journal of China University of Mining & Technology, 5 (2001) 458-462.

[5] H Chen. Single chip microprocessor control for switched reluctance motor drive. KIEE International Transactions on EMECS, 4 (2002) 207-213.

[6] H Chen, W Cheng, G Xie, C Zhang. PID control of a switched reluctance motor drive with intel 80c196kb microcomputer. Proceedings of IEEE Hong Kong Symposium on Robotics and Control, 1 (1999) 304-307. [7] H Chen and T Su. Control of The Switched Reluctance Motor Drive at Four Quadrants Based on Intel

87C196KC Single Chip Microprocessor. Dynamics of Continuous, Discrete and Impulsive Systems, Series B (2005) 306-311.

[8] H Chen and X Zan. Sliding mode and PI control of switched reluctance motor drive. Dynamics of Continuous, Discrete and Impulsive Systems, Series B (2006) 427-431.

AT89C51单片机外文翻译

AT89C51外文翻译 Description The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash Programmable and Erasable Read Only Memory (PEROM). The device is manufactured using Atmel’s high density nonvolatile memory technology and is compatible with the industry standard MCS-51? instruction-set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications. Features ? Compatible with MCS-51? Products ? 4K Bytes of In-System Reprogrammable Flash Memory – Endurance: 1,000 Write/Erase Cycles ? Fully Static Operation: 0 Hz to 24 MHz ? Three-Level Program Memory Lock ? 128 x 8-Bit Internal RAM ? 32 Programmable I/O Lines ? Two 16-Bit Timer/Counters ? Six Interrupt Sources ? Programmable Serial Channel ? Low Power Idle and Power Down Modes The AT89C51 provides the following standard features: 4K bytes of Flash,128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.

步进电机及单片机英文文献及翻译

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会计内部控制中英文对照外文翻译文献(文档含英文原文和中文翻译)

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单片机外文翻译

杭州电子科技大学信息工程学院毕业设计（论文）外文文献翻译毕业设计（论文）题目用单片机实现的数字时钟电路设计文献综述题目单片机控制系统系电子工程专业电子信息科学与技术姓名郭筱楠班级08091911 学号08919115 指导教师王维平

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附录A

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SCM is an integrated circuit chip, is the use of large scale integrated circuit technology to a data processing capability of CPU CPU random access memory RAM, read-only memory ROM, a variety of I / O port and interrupt system, timers / timer functions (which may also include display driver circuitry, pulse width modulation circuit, analog multiplexer, A / D converter circuit) integrated into a silicon constitute a small and complete computer systems. SCM is also known as micro-controller (Microcontroller), because it is the first to be used in industrial control. Only a single chip by the CPU chip developed from a dedicated processor. The first design is by a large number of peripherals and CPU on a chip in the computer system, smaller, more easily integrated into a complex and demanding on the volume control device which. The Z80 INTEL is the first designed in accordance with this idea processor, then on the development of microcontroller and dedicated processors will be parting ways. Are 8-bit microcontroller early or 4 bits. One of the most successful is the INTEL 8031, for a simple, reliable and good performance was a lot of praise. Then developed in 8031 out of MCS51 MCU Systems. SCM systems based on this system until now is still widely used. With the increased requirements of industrial control field, began a 16-bit microcontroller, but not ideal because the cost has not been very widely used. After 90 years with the great development of consumer electronics, microcontroller technology has been a huge increase. With INTEL i960 series, especially the later series of widely used ARM, 32-bit microcontroller quickly replace high-end 16-bit MCU status and enter the mainstream market. The traditional 8-bit microcontroller performance have been the rapid increase capacity increase compared to 80 the number of times. Currently, high-end 32-bit microcontroller clocked over 300MHz, the performance catching the mid-90s dedicated processor, while the average model prices fall to one U.S. dollar, the most high-end [1] model only 10 dollars. Modern SCM systems are no longer only in the development and use of bare metal environment, a large number of proprietary embedded operating system is widely used in the full range of SCM. The handheld computers and cell phones as the core processing of high-end microcontroller can even use a dedicated Windows and Linux operating systems. SCM is more suitable than the specific processor used in embedded systems, so it was up to the application. In fact the number of SCM is the world's largest computer. Modern human life used in almost every piece of electronic and mechanical products will be integrated single chip. Phone, telephone, calculator, home appliances, electronic toys, handheld computers and computer accessories such as a mouse with a 1-2 in both the Department of SCM. Personal computer will have a large number of SCM in the work. General car with more than 40 microcontroller, a complex industrial control systems may even hundreds of single chip at the same time work! SCM is not only far exceeds the number of PC and other computing the sum, or even more than the number of human beings. Single chip, also known as single-chip microcontroller, it is not complete a certain logic chips, but to a computer system integrated into a chip. Equivalent to a

外文翻译---51系列单片机的结构和功能

外文资料翻译英文原文： Structure and function of the MCS-51 series Structure and function of the MCS-51 series one-chip computer MCS-51 is a name of a piece of one-chip computer series which Intel Company produces. This company introduced 8 top-grade one-chip computers of MCS-51 series in 1980 after introducing 8 one-chip computers of MCS-48 series in 1976. It belong to a lot of kinds this line of one-chip computer the chips have such as 8051, 8031, 8751, 80C51BH, 80C31BH,etc., their basic composition, basic performance and instruction system are all the same. 8051 daily representatives- 51 serial one-chip computers . An one-chip computer system is made up of several following parts: (1) One microprocessor of 8 (CPU). (2) At slice data memory RAM (128B/256B),it use not depositing not can reading /data that write, such as result not middle of operation, final result and data wanted to show, etc. (3) Procedure memory ROM/EPROM (4KB/8KB ), is used to preserve the procedure , some initial data and form in slice. But does not take ROM/EPROM within some one-chip computers, such as 8031 , 8032, 80C ,etc.. (4) Four 8 run side by side I/O interface P0 four P3, each mouth can use as introduction, may use as exporting too. (5) Two timer / counter, each timer / counter may set up and count in the way, used to count to the external incident, can set up into a timing way too, and can according to count or result of timing realize the control of the computer. (6) Five cut off cutting off the control (universal asynchronous receiver/transmitter (UART) ), is it realize one-chip computer or one-chip computer and serial communication of computer to use for. (8) Stretch oscillator and clock produce circuit, quartz crystal finely tune electric capacity need outer. Allow oscillation frequency as 12 megahertz now at most. Every the above-mentioned part was joined through the inside data bus .Among them, CPU is a core of the one-chip computer, it is the control of the computer and command center, made up of such parts as arithmetic unit and controller , etc.. The arithmetic unit can carry on 8 persons of arithmetic operation and unit ALU of logic operation while including one, the 1 storing devices temporarily of 8, storing device 2 temporarily, 8's accumulation device ACC, register B and procedure state register PSW, etc. Person who accumulate ACC count by 2 input ends entered of checking etc. temporarily as one operation often, come from person who store 1 operation is it is it make operation to go on to count temporarily , operation result and loop back ACC with another one. In addition, ACC is often regarded as the transfer station of data transmission on 8051 inside. The same as general microprocessor, it is the busiest register. Help remembering that agreeing with a expresses in the order. The controller includes the procedure counter, the order is deposited, the