加法器、减法器的设计 VHDL

实验报告

课程名称电子设计自动化实验（基于FPGA）实验项目加法器、减法器的设计

实验仪器计算机+ Quartus Ⅱ9.1

系别信息与通信工程学院

专业通信工程

班级/学号

学生姓名

实验日期2012、5

成绩_______________________ 指导教师_______________________

加法器、减法器的设计

完成一个8位二进制带符号数的加减电路设计。设计要求如下：通过拨码开关输入两组8位二进制数，最高位为符号位，0表示正数，1表示负数，其余位表示二进制数值。用一按键对加、减方式进行控制，0表示加，1表示减。输出用四位LED数码管显示BCD码。其中LED显示器最高位为符号位。

VHDL代码

LIBRARY IEEE;

USE IEEE.std_logic_1164.all;

USE IEEE.std_logic_arith.all;

USE IEEE.std_logic_unsigned.all;

ENTITY add IS

PORT(a:in std_logic_vector(7 downto 0);

b:in std_logic_vector(7 downto 0);

ctrl:in std_logic;

bcd:out std_logic_vector(15 downto 0));

END ENTITY;

ARCHITECTURE func OF add IS

SIGNAL x:std_logic_vector(9 downto 0);

SIGNAL y:std_logic_vector(9 downto 0);

SIGNAL z:std_logic_vector(9 downto 0);

SIGNAL c:std_logic_vector(8 downto 0);

SIGNAL dec:integer;

BEGIN

yunsuan:BLOCK --运算模块

BEGIN

PROCESS(a)

BEGIN

IF (a(7) = '0') THEN --判断正负

x <= '0'&'0'&a;

ELSE

x(9 downto 8) <= '1'&'1';

x(7 downto 0) <= NOT('0'&a(6 downto 0)) + 1;

END IF;

END PROCESS;

PROCESS(a,ctrl)

BEGIN

IF(ctrl = '0') THEN --控制键为0，则做加法IF(b(7) = '0') THEN

y <= '0'&'0'&b;

ELSE

y <= '1'&'1'&(NOT('0'&b(6 downto 0))+1);

END IF;

ELSE

IF(b(7) = '1') THEN

y <= '0'&'0'&'0'&b(6 downto 0);

ELSE

y <= '1'&'1'&(NOT('0'&b(6 downto 0))+1);

END IF;

END IF;

END PROCESS;

PROCESS(a,b)

BEGIN

IF(a(6 downto 0) = 0) THEN

z <= y;

ELSE IF(b(6 downto 0) = 0) THEN

z <= x;

ELSE

z <= x + y;

END IF;

END IF;

END PROCESS;

PROCESS(z)

BEGIN

IF(z(9) = '1') THEN --判断结果的正负c(7 downto 0) <= NOT z(7 downto 0) + 1;

c(8) <= '1';

ELSE

c(8 downto 0) <= '0'&z(7 downto 0);

END IF;

END PROCESS;

END BLOCK;

bcdout:BLOCK

BEGIN

dec <= CONV_INTEGER(c); --二进制转十进制

PROCESS(c)

BEGIN

CASE c(8) IS --判断最高位正负

WHEN '0' => bcd(15 downto 12) <= "0000";

WHEN '1' => bcd(15 downto 12) <= "0001";

WHEN OTHERS => bcd(15 downto 12) <= NULL;

END CASE;

CASE dec/100 IS --判断百位数字

WHEN 0 => bcd(11 downto 8) <= "0000";

WHEN 1 => bcd(11 downto 8) <= "0001";

WHEN OTHERS => bcd(11 downto 8) <= NULL;

END CASE;

CASE (dec REM 100)/10 IS

WHEN 0 => bcd(7 downto 4) <= "0000";

WHEN 1 => bcd(7 downto 4) <= "0001";

WHEN 2 => bcd(7 downto 4) <= "0010";

WHEN 3 => bcd(7 downto 4) <= "0011";

WHEN 4 => bcd(7 downto 4) <= "0100";

WHEN 5 => bcd(7 downto 4) <= "0101";

WHEN 6 => bcd(7 downto 4) <= "0110";

WHEN 7 => bcd(7 downto 4) <= "0111";

WHEN 8 => bcd(7 downto 4) <= "1000";

WHEN 9 => bcd(7 downto 4) <= "1001";

WHEN OTHERS => bcd(7 downto 4) <= NULL;

END CASE;

CASE dec REM 10 IS

WHEN 0 => bcd(3 downto 0) <= "0000";

WHEN 1 => bcd(3 downto 0) <= "0001";

WHEN 2 => bcd(3 downto 0) <= "0010";

WHEN 3 => bcd(3 downto 0) <= "0011";

WHEN 4 => bcd(3 downto 0) <= "0100";

WHEN 5 => bcd(3 downto 0) <= "0101";

WHEN 6 => bcd(3 downto 0) <= "0110";

WHEN 7 => bcd(3 downto 0) <= "0111";

WHEN 8 => bcd(3 downto 0) <= "1000";

WHEN 9 => bcd(3 downto 0) <= "1001";

WHEN OTHERS => bcd(3 downto 0) <= NULL;

END CASE;

END PROCESS;

END BLOCK;

END ARCHITECTURE;

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——Higashi Q83831295