38译码器实验仿真结果图

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY mux8_1 IS

PORT(add : IN STD_LOGIC_vector(2 downto 0);

i:IN STD_LOGIC_vector(0 to 7);

y: OUT STD_LOGIC);

END mux8_1;

ARCHITECTURE behave OF mux8_1 IS

--SIGNAL sel :STD_LOGIC_vector(2 DOWNTO 0); BEGIN

--sel<=A2 & A1 & A0;

PROCESS(add,i)

BEGIN

CASE add IS

WHEN "000" => y<=i(0);

WHEN "001" => y<=i(1);

WHEN "010" => y<=i(2);

WHEN "011" => y<=i(3);

WHEN "100" => y<=i(4);

WHEN "101" => y<=i(5);

WHEN "110" => y<=i(6);

WHEN "111" => y<=i(7);

WHEN others => NULL;

END CASE;

END PROCESS;

END behave;

三八译码器

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY dec38 IS

PORT (G1, G2A, G2B : IN STD_LOGIC;

add : IN STD_LOGIC_vector(2 downto 0);

Y : OUT STD_LOGIC_VECTOR(0 TO 7)); END dec38;

ARCHITECTURE dataflow1 OF dec38 IS

SIGNAL YI: STD_LOGIC_VECTOR(0 TO 7);

--SIGNAL add: STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN

--add <= c & b & a;

WITH add SELECT

YI <= "01111111" WHEN "000",

"10111111" WHEN "001",

"11011111" WHEN "010",

"11101111" WHEN "011",

"11110111" WHEN "100",

"11111011" WHEN "101",

"11111101" WHEN "110",

"11111110" WHEN "111",

"11111111" WHEN OTHERS;

Y <= YI WHEN (G1 AND NOT G2A AND NOT G2B) ='1'

ELSE "11111111";

END dataflow1;

半加器

LIBRARY IEEE; --半加器描述(1)：布尔方程描述方法USE IEEE.STD_LOGIC_1164.ALL;

ENTITY h_adder IS

PORT (a, b : IN STD_LOGIC;

co, so : OUT STD_LOGIC);

END ENTITY h_adder;

ARCHITECTURE fh1 OF h_adder is

BEGIN

so <= NOT(a XOR ( NOT b)) ;

co <= a AND b;

END ARCHITECTURE fh1;

系列信号检测（密码核对器）

library IEEE; --1110010序列检测

use IEEE.std_logic_1164.all;

ENTITY xljc IS

PORT ( din,clk,clr : IN STD_LOGIC; --串行数据输入/工作时钟/复位信号ab :OUT STD_LOGIC_vector(3 downto 0));--输出检测结果

END ENTITY xljc;

ARCHITECTURE one OF xljc IS

signal q :integer range 0 to 7;

signal d :STD_LOGIC_vector(6 downto 0);--七位待检测数据预置数

BEGIN

d<="1110010"; --七位待检数据输入预置

process(clk,clr)

begin

if clr='1' then q<=0; --复位

elsif clk'event and clk='1' then --时钟上升沿到来

case q is

WHEN 0 => if din=d(6) then q<=1; ELSE q<=0;end if;

WHEN 1 => if din=d(5) then q<=2; ELSE q<=0;end if;

WHEN 2 => if din=d(4) then q<=3; ELSE q<=0;end if;

WHEN 3 => if din=d(3) then q<=4; ELSE q<=0;end if;

WHEN 4 => if din=d(2) then q<=5; ELSE q<=0;end if;

WHEN 5 => if din=d(1) then q<=6; ELSE q<=0;end if;

WHEN 6 => if din=d(0) then q<=7; ELSE q<=0;end if;

WHEN OTHERS =>q<=0;

end case;

end if;

end process;

process(q)

begin

if q=7 then ab<="1010"; else

ab<="1011";

end if;

end process; END ARCHITECTURE one ;