单片机设计外文文献翻译(含中英文)

附录A 外文翻译——AT89S52/AT89S51技术手册

AT89S52译文

主要性能

与MCS-51单片机产品兼容

8K字节在系统可编程Flash存储器

1000次擦写周期

全静态操作：0Hz～33Hz

三级加密程序存储器

32个可编程I/O口线

三个16位定时器/计数器

八个中断源

全双工UART串行通道

低功耗空闲和掉电模式

掉电后中断可唤醒

看门狗定时器

双数据指针

掉电标识符

功能特性描述

AT89S52是一种低功耗、高性能CMOS8位微控制器，具有8K在系统可编程Flash 存储器。使用Atmel公司高密度非易失性存储器技术制造，与工业80C51产品指令和引脚完全兼容。片上Flash 允许程序存储器在系统可编程，亦适于常规编程器。在单芯片上，拥有灵巧的8位CPU和在系统可编程Flash，使得AT89S52为众多嵌入式控制应用系统提供高灵活、超有效的解决方案。AT89S52具有以下标准功能：8k字节Flash，256字节RAM，32位I/O口线，看门狗定时器，2个数据指针，三个16位定时器/计数器，一个6向量2级中断结构，全双工串行口，片内晶振及时钟电路。另外，AT89S52可降至0Hz静态逻辑操作，支持2种软件可选择节电模式。空闲模式下，CPU停止工作，允许RAM、定时器/计数器、串口、中断继续工作。掉电保护方式下，RAM内容被保存，振荡器被冻结，单片机一切工作停止，直到下一个中断或硬件复位为止。

引脚结构

方框图

VCC : 电源

GND :地

P0口：P0口是一个8位漏极开路的双向I/O口。作为输出口，每位能驱动8个TTL逻辑电平。对P0端口写“1”时，引脚用作高阻抗输入。当访问外部程序和数据存储器时，P0口也被作为低8位地址/数据复用。在这种模式下，P0具有内部上拉电阻。

在flash编程时，P0口也用来接收指令字节；在程序校验时，输出指令字节。程序校验时，需要外部上拉电阻。

P1口：P1 口是一个具有内部上拉电阻的8位双向I/O 口，p1 输出缓冲器能驱动4个TTL 逻辑电平。对P1端口写“1”时，内部上拉电阻把端口拉高，此时可以作为输入口使用。作为输入使用时，被外部拉低的引脚由于内部电阻的原因，将输出电流（IIL）。此外，P1.0和P1.2分别作定时器/计数器2的外部计数输入（P1.0/T2）和时器/计数器2的触发输入（P1.1/T2EX），具体如下表所示。在flash编程和校验时，P1口接收低8位地址字节。

P2 口：P2 口是一个具有内部上拉电阻的8 位双向I/O 口，P2输出缓冲器能驱动4个TTL 逻辑电平。对P2端口写“1”时，内部上拉电阻把端口拉高，此时可以作为输入口使用。作为输入使用时，被外部拉低的引脚由于内部电阻的原因，将输出电流（IIL）。在访问外部程序存储器或用16位地址读取外部数据存储器（例如执行MOVX @DPTR）时，P2口送出高八位地址。在这种应用中，P2口使用很强的内部上拉发送1。在使用8位地址（如MOVX @RI）访问外部数据存储器时，P2口输出P2锁存器的内容。

在flash编程和校验时，P2口也接收高8位地址字节和一些控制信号。

P3 口：P3口是一个具有内部上拉电阻的8 位双向I/O 口，p2输出缓冲器能驱动4个TTL 逻辑电平。对P3端口写“1”时，内部上拉电阻把端口拉高，此时可以作为输入口使用。作为输入使用时，被外部拉低的引脚由于内部电阻的原因，将输出电流（IIL）。P3口亦作为AT89S52特殊功能（第二功能）使用，如下表所示。在flash编程和校验时，P3口也接收一些控制信号。

RST: 复位输入。晶振工作时，RST脚持续2个机器周期高电平将使单片机复位。看门狗计时完成后，RST脚输出96个晶振周期的高电平。特殊寄存器AUXR(地址8EH)上的DISRTO位可以使此功能无效。DISRTO默认状态下，复位高电平有效。

ALE/PROG：地址锁存控制信号（ALE）是访问外部程序存储器时，锁存低8位地址的输出脉冲。在flash编程时，此引脚也用作编程输入脉冲。

在一般情况下，ALE 以晶振六分之一的固定频率输出脉冲，可用来作为外部定时器或时钟使用。然而，特别强调，在每次访问外部数据存储器时，ALE脉冲将会跳过。

如果需要，通过将地址为8EH的SFR的第0位置“1”，ALE操作将无效。这一位置“1”，ALE 仅在执行MOVX 或MOVC指令时有效。否则，ALE 将被微弱拉高。这个ALE 使能标志位（地址为8EH的SFR的第0位）的设置对微控制器处于外部执行模式下无效。

PSEN:外部程序存储器选通信号是外部程序存储器选通信号。

当 AT89S52从外部程序存储器执行外部代码时，在每个机器周期被激活两次，而在访问外部数据存储器时，将不被激活。

EA/VPP:访问外部程序存储器控制信号。为使能从0000H 到FFFFH的外部程序存储器读取指令，必须接GND。

为了执行内部程序指令，应该接VCC。

在flash编程期间，也接收12伏VPP电压。

XTAL1:振荡器反相放大器和内部时钟发生电路的输入端。

XTAL2:振荡器反相放大器的输出端。

存储器结构

MCS-51器件有单独的程序存储器和数据存储器。外部程序存储器和数据存储器都可以64K寻址。

程序存储器：如果EA引脚接地，程序读取只从外部存储器开始。

对于89S52，EA如果接VCC，程序读写先从内部存储器（地址为0000H～1FFFH）开始，接着从外部寻址，寻址地址为：2000H~FFFFH。

中断

AT89S52有6个中断源：两个外部中断和，三个定时中断（定时器0、1、2）和一个串行中断。这些中断每个中断源都可以通过置位或清除特殊寄存器IE中的相关中断允许控制位分别使得中断源有效或无效。IE还包括一个中断允许总控制位EA，它能一次禁止所有中断。IE.6位是不可用的。对于AT89S52，IE.5位也是不能用的。用户软件不应给这些位写1。它们为AT89系列新产品预留。

定时器2可以被寄存器T2CON中的TF2和EXF2的或逻辑触发。程序进入中断服务后，这些标志位都可以由硬件清0。实际上，中断服务程序必须判定是否是TF2 或EXF2激活中断，标志位也必须由软件清0。

定时器0和定时器1标志位TF0 和TF1在计数溢出的那个周期的S5P2被置位。它们的值一直到下一个周期被电路捕捉下来。然而，定时器2的标志位TF2在计数溢出的那个周期的S2P2被置位，在同一个周期被电路捕捉下来。

AT89S51译文

AT89S51 (8位微控制单片机，片内含4K bytes可系统编程的存储器)

AT89S51是美国ATMEL公司生产的低功耗，高性能CMOS 8位单片机，片内含4k bytes的可系统编程的Flash只读程序存储器，器件采用ATMEL公司的高密度、非易失性存储技术生产，兼容标准8051指令系统及引脚。它集Flash程序存储器既可在线编程（ISP)也可用传统方法进行编程及通用8位微处理器于单片芯片中，ATMEL公司的功能强大，低价位AT89S51单片机可为您提供许多高性价比的应用场介，可灵活应用于各种控制领域。

主要性能参数：

·与MCS-51 产品指令系统完全兼:容

·4k字节在线系统编程(ISP) Flash闪速存储器

·1000次擦写周期

·4. 0---5. 5V的工作电压范围

·全静态工作模式：0Hz---33MHz

·三级程序加密锁

·128×8字节内部RAM

·32个可编程I/O口线

·2个16位定时/计数器

·6个中断源

·全双工串行UART通道

·低功耗空闲和掉电模式

·中断可从空闲模式唤醒系统

·看门狗(WDT)及双数据指针

·掉电标识和快速编程特性

·灵活的在线系统编程(ISP一字节或页写模式)

功能特性概述：

AT89S51提供以下标准功能：4k字节Flash闪速存储器，128字节内部RAM， 32个I/O口线，看门狗（WDT），两个数据指针，两个16位定时/计数器，一个5向量两级中断结构，一个全双工串行通信口，片内振荡器及时钟电路。同时，AT89S51可降至0Hz的静态逻辑操作，并支持两种软件可选的节电工作模式。空闲方式停止CPU的工作，但允许RAM，定时/计数器，串行通信口及中断系统继续工作。掉电方式保存RAM中的内容，但振荡器停止工作并禁止其它所有部件工作直到下一个硬件复位。

引脚功能说明：

·Vcc：电源电压

·GND：地

·P0口：P0口是一组8位漏极开路型双向I/O口，也即地址/数据总线复用口。作为输出口用时，每位能驱动8个TTL逻辑门电路，对端口写‘1’可作为高阻抗输入端用。

在访问外部数据存储器或程序存储器时，这组口线分时转换地址(低8位)和数据总线复用，在访问期间激活内部上拉电阻。

在Flash编程时，P0 口接收指令字节，而在程序校验时，输出指令字节，校验时，要求外接上拉电阻。

·P1口：P1是一个带内部上拉电阻的8位双向I/O口，P1的输出缓冲级可驱动(吸收或输出电流)4个TTL逻辑门电路。对端口写‘1’，通过内部的上拉电阻把端口拉到高电平，此时可作输入口。作输入口使用时，囚为内部存在上拉电阻，某个引脚被外部信号拉低时会输出一个电流(In)。

Flash编程和程序校验期间 P 1接收低8位地址。

·P2口：P2是一个带有内部上拉电阻的8位双向I/O口，P2的输出缓冲级可驱动(吸收或输出电流)4个TTL逻辑门电路。对端口写‘1’，通过内部的上拉电阻把端口拉到高电平，此时可作输入口，作输入口使用时，囚为内部存在上拉电阻，某个引脚被外部信号拉低时会输出一个电流(In)。在访问外部程序存储器或16位地址的外部数据存储器(例如执行MOVX @DPTR指令)时，P2口送出高8位地址数据。在访问8位地址的外部数据存储器(如执行MOVX @Ri指令)时，P2口线卜的内容(也即特殊功能寄存器（SFR)区中P2寄存器的内容)，在整个访问期间不改变。

Flash编程或校验时，P2亦接收高位地址和其它控制信号。

·P3口：P3口是一组带有内部上拉电阻的8位双向I/O口。P3口输出缓冲级可驱动(吸收或输出电流)4个TTL逻辑门电路。对P3 口写入“1”时，它们被内部上拉电阻拉高并可作为输入端口。作输入端时，被外部拉低的P3 口将用上拉电阻输出电流（In）。

P3口除了作为一般的I/O口线外，更重要的用途是它的第二功能。

P3 口还接收一些用于Flash闪速存储器编程和程序校验的控制信号。

·RST：复位输入。当振荡器工作时，RST引脚出现两个机器周期以上高电平将使单片机复位。WDT 溢出将使该引脚输出高电平，设置SFR AUXR 的DISRTO位（地址8EH）可打开或关闭该功能。DISRTO 位缺省为RESET输出高电平打开状态。

·ALE/PROG：当访问外部程序存储器或数据存储器时，ALE(地址锁存允许)输出脉冲用于锁存地址的低8位字节。即使不访问外部存储器，ALE仍以时钟振荡频率的1/6输出固定的正脉冲信号，囚此它可对外输出时钟或用于定时目的。要注意的是：每当访问外部数据存储器时将跳过一个ALE脉冲。对Flash存储器编程期间，该引脚还用于输入编程脉冲（PROG）。

如有必要，可通过对特殊功能寄存器（SFR)区中的8EH单元的D0位置位，可禁正ALE操作。该位置位后，只有一条MOVX和MOVC指令ALE才会被激活。此外，该引脚会被微弱拉高，单片机执行外部程序时，应设置ALE无效。

·PSEN：程序储存允许(PSEN)输出是外部程序存储器的读选通信号，当AT89S51由外部程序存储器取指令(或数据)时，每个机器周期两次PSEN有效，即输出两个脉冲。当访问外部数据存储器，没有两次有效的PSEN信号。

·EA/VPP：外部访问允许。欲使CPU仅访问外部程序存储器(地址为0000H-FFFFH), EA端必须保持低电平(接地)。需注意的是：如果加密位LB1被编程，复位时内部会锁存EA端状态。

如EA端为高电平(接Vcc端)，CPU则执行内部程序存储器中的指令。

Flash存储器编程时，该引脚加上+12 V的编程电压Vpp。

·XTAL 1：振荡器反相放大器及内部时钟发生器的输入端。

·XTAL2：振荡器反相放大器的输出端。

·特殊功能寄存器：

特殊功能寄存器的于片内的空间分布的这些地址并没有全部占用，没有占用的地址亦不可使用，读这些地址将得到一个随意的数值。而写这些地址单元将不能得到预期的结果。

·中断寄存器：

各中断允许控制位于IE寄存器，5个中断源的中断优先级控制位于IP寄存器。

·双时钟指针寄存器：

为更方便地访问内部和外部数据存储器，提供了两个16位数据指针寄存器：DP0位于SFR(特殊功能寄存器)区块中的地址82H, 83H和DP1位于地址84H, 85H，当SFR中的位DPS=0选择DP0，而DPS=1则选择DP1。用户应在访问相应的数据指针寄存器前初始化DPS位。

·电源空闲标志：

电源空闲标志（POF）在特殊功能寄存器SFR中PCON的第4位(PCON.4}，电源打开时POF置‘1’，它可由软件设置睡眠状态并不为复位所影响。

·程序存储器：

如果EA引脚接地(GND)，全部程序均执行外部存储器。

在AT89S51,假如EA接至Vcc(电源+)，程序首先执行地址从0000H-OFFFH （4KB）内部程序存储器，而执行地址为1000H-FFFFH (60KB)的外部程序存储器。

·数据存储器：

AT89S51的具有128字节的内部RAM，这128字节可利用直接或间接寻址方式访问，堆栈操作可利用间接寻址方式进行，128字节均可设置为堆栈区空间。

·看门狗定时器(WDT)：

WDT是为了解决CPU程序运行时可能进入混乱或死循环而设置，它由一个14bit计数器和看门狗复位SFR (WDTRST)构成。外部复位时，WDT默认为关闭状态，要打开WDT，用户必须按顺序将01EH和0E1H写到WDTRST寄存器（SFR地址为OA6H},当启动了WDT，它会随晶体振荡器在每个机器周期计数，除硬件复位或WDT溢出复位外没有其它方法关闭WDT，当WDT溢出，将使RSF引脚输出高电平的复位脉冲。

·定时器0和定时器1：

定时器0和1都是一个16位定时/计数器。

AT89S52原文

Features

? Compatible with MCS-51? Products

? 8K Bytes of In-System Programmable (ISP) Flash Memory

? 1000 Write/Erase Cycles

? Fully Static Operation: 0 Hz to 33 MHz

? Three-level Program Memory Lock

? 256 x 8-bit Internal RAM

? 32 Programmable I/O Lines

? Three 16-bit Timer/Counters

? Eight Interrupt Sources

? Full Duplex UART Serial Channel

? Low-power Idle and Power-down Modes

? Interrupt Recovery from Power-down Mode

? Watchdog Timer

? Dual Data Pointer

? Power-off Flag

Description

The AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with 8K bytes of

in-system programmable Flash memory. The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry standard 80C51 instruction set and pinout. The on-chip Flash allows the programmemory to be reprogrammed in-system or by a conventional nonvolatile memory programmer.By combining a versatile 8-bit CPU with in system programmable Flash on a monolithicchip, the Atmel AT89S52 is a powerful icrocontroller which provides a highly-flexible and cost-effective solution to many embedded control applications.The AT89S52 provides the following tandard features: 8K bytes of Flash, 256 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator,and clock circuitry. In addition, the AT89S52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes.The Idle Mode stops the CPU

while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset.

Pin Configurations

Block Diagram

Pin Description

VCC

Supply voltage.

GND

Ground.

Port 0

Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high- impedance Inputs.

Port 0 can also be configured to be the multiplexed loworder address/data bus during ccesses to external program and data memory. In this mode, P0 has int -ernal pullups.

Port 0 also receives the code bytes during Flash programming and outputs the code bytes dur -ing

program verification.External pullups are required during program veri-fication.

Port 1

Port 1 is an 8-bit bidirectional I/O port with internal pullups.The Port 1 output buffers can sink/source four TTL inputs.When 1s are written to Port 1 pins, they are pulled high bythe internal pullups and can be used as inputs. As inputs,Port 1 pins that are externally being pulled low will sourcecurrent (IIL) because of the internal pullups.

In addition, P1.0 and P1.1 can be configured to be the ti -mer/counter 2 exte- rnal count input (P1.0/T2) and the timer/counter 2 trigger input(P1.1/T2EX), respectively, as shown in the following table.

Port 1 also receives the low-order address bytes during Flash programming and verification.

Port 2

Port 2 is an 8-bit bidirectional I/O port with internal pullups.The Port 2 output buffers can

sink/source four TTL inputs.When 1s are written to Port 2 pins, they are pulled high bythe internal pullups and can be used as inputs. As inputs,Port 2 pins that are externally being pulled low will sourcecurrent (IIL) because of the internal pullups.

Port 2 emits the high-order address byte during fetches from external program memory and during accesses toexternal data memory that use 16-bit ddresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.

Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.

Port 3

Port 3 is an 8-bit bidirectional I/O port with internal pullups.The Port 3 output buffers can sink/source

four TTL inputs.When 1s are written to Port 3 pins,they are pulled high by the internal pullups and can be used as inputs. As inputs,

Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.

Port 3 also serves the functions of various special featuresof the AT89S52, as shown in the following table.

Port 3 also receives some control signals for Flash programming and verification.

RST

Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives High for 96 oscillator periods after the Watchdog times out.The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO,the RESET HIGH out feature

is enabled.

Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input during Flash programming.

In normal operation, ALE is emitted at a constant rate of1/6 the oscillator frequ- ency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory.

If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin isweakly pulled high. Setting the ALE-disable bit has no effect if the microco- ntroller is in external execution mode.

Program Store Enable is the read strobe to external program memory.

When the AT89S52 is executing code from external program memory,is activated twice each machine cycle, except that twoactivations are skipped during each access to external data memory.

External Access Enable. must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmedwill be ternally latched on reset.should be strapped to VCC for internal rogram executions.This pin also receives the 12-volt programming enable voltage(VPP) during Flash programming.

XTAL1

Input to the inverting oscillator amplifier and input to the nternal clock operating circuit.

XTAL2

Output from the inverting oscillator amplifier.

Special Function Registers

A map of the on-chip memory area called the Special FunctionRegister (SFR) space is shown in Table

1.Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.

User software should not write 1s to these unlisted locations,since they may be used in future products to invokenew features. In that case, the reset or nactive values of the new bits will always be 0.

Timer 2 Registers: Control and status bits are contained in registers T2CON (shown in Table 2) and

T2MOD (shown in Table 3) for Timer 2. The register pair (RCAP2H , RCAP2L) are the Capture/Reload registers for Timer 2 in 16-bit capture mode or 16-bit auto-reload mode.

Interrupt Registers: The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the six interrupt sources in the IP register.

Timer 2 Operating Modes

In the Counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. To nsure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle.

Interrupts

The AT89S52 has a total of six interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. These interrupts are all shown in Figure 10. Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which

disables all interrupts at once. Note that Table 5 shows that bit position IE.6 is unimplemented. In the AT89S52, bit position IE.5 is also unimplemented.

User software should not write 1s to these bit positions, since they may be used in future AT89 products. Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register T2CON. Neither of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt, and that bit will have to be cleared in software. The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers overflow. The values are then polled by the circuitry in the next cycle. However, the Timer 2 flag, TF2, is set at S2P2 and is polled in the same cycle in which the timer overflows.

AT89S51原文

The AT89S51 is a low-power, high-performance CMOS 8-bit microcontroller with 4K bytesof In-System Programmable Flash memory. The device is manufactured using Atmel's high-density nonvolatile memory technology and is compatible with the industry-standard 80C51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory

programmer. By combining a versatile 8-bit CPU with In-System Programmable Flash on a monolithic chip, the Atmel AT89S51 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications.

Features：

.Compatible with MCS.-51 Products

4K Bytes of In-System Programmable (ISP) Flash Memory

一Endurance: 1000 Write/Erase Cycles

4.0V to

5.5V Operating Range

Fully Static Operation: 0 Hz to 33 MHz

Three-level Program Memory Lock

128 x 8-bit Internal RAM

32 Programmable I/O Lines

Two 16-bit Timer/Counters

Six Interrupt Sources

Full Duplex UART Serial Channel

Low-power Idle and Power-down Modes

Interrupt Recovery from Power-down Mode

Watchdog Timer

Dual Data Pointer

Power-off Flag

Fast Programming Time

Flexible ISP Programming (Byte and Page Mode)

Green (Pb/Halide-free) Packaging Option

The AT89S51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, two 16-bit timer/counters, a five-vector two一level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM contents but freezes the

oscillator, disabling all other chip functions until the next external interrupt or hardware reset.

VCC：

Supply voltage (all packages except 42-PDIP).

GND：

Ground (all packages except 42一PDIP; for 42-PDIP GND connects only the logic core and the embedded program memory).

VDD：

Supply voltage for the 42-PDIP which connects only the logic core and the embedded program memory. PWRVDD：

Supply voltage for the 42-PDIP which connects only the I/O Pad Drivers. The application board MUST connect both VDD and PWRVDD to the board supply voltage.

PWRGND：

Ground for the 42一PDIP which connects only the I/O Pad Drivers. PWRGND and GND are weakly connected through the common silicon substrate, but not through any metal link. The application board MUST connect both GND and PWRGND to the board ground.

Port 0：

Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high一impedance inputs.

Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, PO has internal pull-ups.

Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pull-ups are required during program verification.

Port 1：

Port 1 is an 8一bit bi-directional I/O port with internal pull一ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pull一ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (lip) because of the internal pull一ups.

Port 2：

Port 2 is an 8一bit bi-directional I/O port with internal pull一ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pull一

ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (lip) because of the internal pull一ups.

Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX@DPTR). In this application, Port 2 uses strong internal pull一ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX@RI), Port 2 emits the contents of the P2 Special Function Register.

Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.

Port 3：

Port 3 is an 8一bit bi-directional I/O port with internal pull一ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pull一ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (lip) because of the pull-ups.

Port 3 receives some control signals for Flash programming and verification.

Port 3 also serves the functions of various special features of the AT89S51，as shown in the following table. RST：

Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives High for 98 oscillator periods after the Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO, the RESET HIGH out feature is enabled.

ALE/PROG：

Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may beused for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory.

If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.

PSEN：

Program Store Enable (PSEN) is the read strobe to external program memory.

When the AT89S51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. EA/VPP：

External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at OOOOH up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.

EA should be strapped to Vcc for internal program executions.

This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming.

XTAL1：

Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

XTAL2：

Output from the inverting oscillator amplifier

Special Function Registers：

Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.

User software should not write 1 s to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0.

Interrupt Registers:

The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the five interrupt sources in the IP register.

Dual Data Pointer Registers:

To facilitate accessing both internal and external data memory, two banks of 16-bit Data Pointer Registers are provided: DPO at SFR address locations 82H-83H and DP1 at 84H-85H.Bit DPS=0 in SFR AUXR1 selects DPO and DPS=1 selects DP1. The user should ALWAYS initialize the DPS bit to the appropriate value before accessing the respective Data Pointer Register.

Power Off Flag:

The Power Off Flag (POF) is locat ed at bit 4 (PCON.4) in the PCON SFR. POF is set to "1”during power up. It can be set and rest under software control and is not affected by reset.

Memory Organization：

MCS-51 devices have a separate address space for Program and Data Memory. Up to 64K bytes each of external Program and Data Memory can be addressed.

Program Memory：

If the EA pin is connected to GND, all program fetches are directed to external memory. On the AT89S51，if EA is connected to Vcc, program fetches to addresses OOOOH through FFFH are directed to internal memory and fetches to addresses 1000H through FFFFH are directed to external memory.

Data Memory：

The AT89S51 implements 128 bytes of on-chip RAM. The 128 bytes are accessible via direct and indirect addressing modes. Stack operations are examples of indirect addressing, so the 128 bytes of data RAM are available as stack space.

Watchdog Timer (One-time Enabled with Reset-out)：

The WDT is intended as a recovery method in situations where the CPU may be subjected to software upsets. The WDT consists of a 14一bit counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user must write 01 EH and OE1 H in sequence to the WDTRST register (SFR location OA6H). When the WDT is enabled, it will increment every machine cycle while the oscillator is running. The WDT timeout period is dependent on the external clock frequency. There is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT overflows, it will drive an output RESET HIGH pulse at the RST pin.

Timer 0 and 1：

Timer 0 and Timer 1 is a 16-bit Timer/Counter