基于单片机的智能晾衣架控制系统的设计与实现外文文献原稿和译文

外文文献原稿和译文

原稿

The Description of AT89S51

1 General Description

The AT89S51 is a low-power, high-performance CMOS 8-bit microcontroller with 4K bytes of In-System Programmable Flash memory. The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard 80C51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with In-System Programmable Flash on a monolithic chip, the Atmel AT89S51 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications.

The AT89S51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, two 16-bit timer/counters, a five-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes.

The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next external interrupt or hardware reset.

2 Ports

Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pull-ups. Port 0 also receives the code bytes during Flash

programming and outputs the code bytes during program verification. External pull-ups are required during program verification.

Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (I IL) because of the internal pull-ups.

Port 1 also receives the low-order address bytes during Flash programming and verification.

Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (I IL) because of the internal pull-ups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.

Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (I IL) because of the pull-ups. Port 3 receives some control signals for Flash programming and verification. Port 3 also serves the functions of various special features of the AT89S51, as shown in the

following table.

3 Special Function Registers

A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 3-1.

0F0H 0F7H

0E8H 0EFH

0E0H 0E7H

0D8H 0DFH

0D0H 0D7H

0C8H 0CFH 0C0H 0C7H 0B8H 0BFH 0B0H 0B7H 0A8H 0AFH

0A0H

0A7H

98H 9FH 90H 97H 88H 8FH

80H

87H

Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.

User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0.

Interrupt Registers: The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the five interrupt sources in the IP register.

Table 3-2. AUXR:Auxiliary Register

AUXR Address=8EH Reset Value=XXX00XX0b

Bit

Reserved for future expansion

DISALE Disable/Enable ALE

DISALE

Operating Mode

0 ALE is emitted at a constant rate of 1/6 the oscillator frequency

1 ALE is active only during a MOVX or MOVC instruction DISRTO Disable/Enable Reset-out

DISRTO

0 Reset pin is driven High after WDT times out

1 Reset pin is input only

WDIDLE Disable/Enable WDT in IDLE mode

WDIDLE

0 WDT continues to count in IDLE mode

1 WDT halts counting in IDLE mode

Dual Data Pointer Registers: To facilitate accessing both internal and external data memory, two banks of 16-bit Data Pointer Registers are provided: DP0 at SFR address locations 82H-83H and DP1 at 84H-85H. Bit DPS = 0 in SFR AUXR1 selects DP0 and DPS = 1 selects DP1. The user should always initialize the DPS bit to the appropriate value before accessing the respective Data Pointer Register.

Power Off Flag: The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF is set to “1” during power up. It can be set and rest under software control and is not affected by reset.

4 Memory Organization

MCS-51 devices have a separate address space for Program and Data Memory. Up to 64K bytes each of external Program and Data Memory can be addressed.

4.1 Program Memory

If the EA pin is connected to GND, all program fetches are directed to external memory. On the AT89S51, if EA is connected to V CC, program fetches to addresses 0000H through FFFH are directed to internal memory and fetches to addresses 1000H through FFFFH are directed to external memory.

4.2 Data Memory

The AT89S51 implements 128 bytes of on-chip RAM. The 128 bytes are accessible via direct and indirect addressing modes. Stack operations are examples of indirect addressing, so the 128 bytes of data RAM are available as stack space.

5 Watchdog Timer (One-time Enabled with Reset-out)

The WDT is intended as a recovery method in situations where the CPU may be subjected to software upsets. The WDT consists of a 14-bit counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To

enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, it will increment every machine cycle while the oscillator is running. The WDT timeout period is dependent on the external clock frequency. There is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT overflows, it will drive an output RESET HIGH pulse at the RST pin.

5.1 Using the WDT

To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, the user needs to service it by writing 01EH and 0E1H to WDTRST to avoid a WDT overflow. The 14-bit counter overflows when it reaches 16383 (3FFFH), and this will reset the device. When the WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at least every 16383 machine cycles. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is a write-only register. The WDT counter cannot be read or written. When WDT overflows, it will generate an output RESET pulse at the RST pin. The RESET pulse duration is 98xTOSC, where TOSC = 1/FOSC. To make the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset.

5.2 WDT DURING Power-down and Idle

In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-down mode, the user does not need to service the WDT. There are two methods of exiting Power-down mode: by a hardware reset or via a level-activated external interrupt, which is enabled prior to entering Power-down mode. When Power-down is exited with hardware reset, servicing the WDT should occur as it normally does whenever the AT89S51 is reset. Exiting Power-down with an interrupt is significantly different. The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service for the interrupt used to exit Power-down mode. To ensure that the WDT does not overflow within a few states of exiting Power-down, it

is best to reset the WDT just before entering Power-down mode. Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine whether the WDT continues to count if enabled. The WDT keeps counting during IDLE (WDIDLE bit = 0) as the default state. To prevent the WDT from resetting the AT89S51 while in IDLE mode, the user should always set up a timer that will periodically exit IDLE, service the WDT, and reenter IDLE mode.

With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the count upon exit from IDLE.

6.Interrupts

The AT89S51 has a total of five interrupt vectors: two external interrupts (INT0 and INT1), two timer interrupts (Timers 0 and 1), and the serial port interrupt. These interrupts are all shown in Figure 6-1. Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once.

Note that Table 6-1 shows that bit positions IE.6 and IE.5 are unimplemented. User software should not write 1s to these bit positions, since they may be used in future AT89 products. The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers overflow. The values are then polled by the circuitry in the next cycle.

Figure 6-1 Interrupt Sources

7 Oscillator Characteristics

XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that can be configured for use as an on-chip oscillator, as shown in Figure 7-1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven, as shown in Figure 7-2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.

Figure 7-1 Oscillator Connections

Note: pF

,1±

=for Crystals

2

pF

30

C

C10

=for Ceramic Resonators

40±

pF10

pF

Figure 7-2 External Clock Drive Configuration

8 Idle Mode

In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special function registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset.

Note that when idle mode is terminated by a hardware reset, the device normally resumes pro-gram execution from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when idle mode is terminated by a reset, the instruction following the one that invokes idle mode should not write to a port pin or to external memory.

9 Power-down Mode

In the Power-down mode, the oscillator is stopped, and the instruction that invokes Power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the Power-down mode is terminated. Exit from Power-down mode can be initiated either by a hardware reset or by activation of an enabled external interrupt (INT0 or INT1). Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.

译文

AT89S51概述

1 一般概述

该AT89S51是一个低功耗，高性能CMOS 8位微控制器,可在4K字节的系统内编程的闪存存储器。该设备是采用Atmel的高密度、非易失性存储器技术和符合工业标准的80C51指令集和引脚。芯片上的Flash程序存储器在系统中可重新编程或常规非易失性内存编程。通过结合通用8位中央处理器的系统内可编程闪存的单芯片， AT89S51是一个功能强大的微控制器提供了高度灵活的和具有成本效益的解决办法，可在许多嵌入式控制中应用。

在AT89S51提供以下标准功能： 4K字节的Flash闪存， 128字节的RAM ，32个 I / O线，看门狗定时器，两个数据指针，两个16位定时器/计数器， 5向量两级中断结构，全双工串行端口，片上振荡器和时钟电路。此外， AT89S51设计了可降至零频率的静态逻辑操作和支持两种软件可选的节电工作模式。

在空闲模式下停止CPU的工作，但允许RAM 、定时器/计数器、串行接口和中断系统继续运行。掉电模式保存RAM中的内容，停止振荡器工作并禁止其它所有部件工作，直到下一个外部中断或硬件复位。

2 端口

P0端口是一个8位漏极开路双向I / O端口。作为一个输出端口，每个引脚可驱动8个TTL输入。对端口写“1”可作为高阻抗输入端用。在访问外部程序和数据存储器时，P0端口也可以配置为复低阶地址/数据总线。在访问期间激活内部上拉电阻。在Flash编程时，PO端口接收指令字节，而在程序校验时，输出指令字节，同时要求外接上拉电阻。

P1端口是一个带内部上拉电阻的8位双向I /O端口。P1端口的输出缓冲级可以驱动四个TTL输入。对端口写“1”，通过内部的上拉电阻把端口拉到高电平，此时可作为输入口。作为输入口时，因为内部存在上拉电阻，某个引脚被外

），Flash编程和程序校验期间，P1接收低8部信号拉低时会输出一个电流（I

IL

位地址。

P2端口是一个带有内部上拉电阻的8位双向I/O端口。P2端口的输出缓冲级可驱动（吸收或输出电流）4个TTL输入。对端口写“1”，通过内部的上拉电阻把端口拉到高电平，此时可作输入口。当作输入口使用时，因为内部存在上

）。在访问外部程序存拉电阻，某个引脚被外部信号拉低时会输出一个电流（I

IL

储器或16位地址的外部数据存储器（例如执行 MOVX @ DPTR指令）时，P2端口送出高8位地址数据。在访问8位地址的外部数据存储器（例如执行MOVX@Ri 指令）时，P2端口上的内容（即特殊功能寄存器（SFR)区中P2寄存器的内容），在整个访问期间不变。Flash编程或校验时，P2也可接收高位地址和其它控制信号。

P3端口是一组带有内部上拉电阻的8位双向I/O端口。P3端口输出缓冲级可驱动（吸收或输出电流）4个TTL逻辑门电路。对P3端口写入“1”时，他们被内部上拉电阻拉高并作为输入端口。当作输入端时，被外部拉低的P2端口将

）．Ｐ３端口还接收一些用于Flash闪存编程和程序校用上拉电阻输出电流（I

IL

验的控制信号。P3端口可以采用AT89S51的

各种特殊功能，如下表所示。

3 特殊功能寄存器

特殊功能寄存器（SFR）的片内空间分布如表3-1所示。

表3-1 AT89S51特殊功能寄存器分布图及复位值

0F0H 0F7H

0E8H 0EFH

0E0H 0E7H

0D8H 0DFH

0D0H 0D7H

0C8H 0CFH

0C0H 0C7H

0B8H 0BFH

0B0H 0B7H

0A8H 0AFH

0A0H 0A7H

98H 9FH

90H 97H

88H 8FH 80H 87H 值得注意的是，这些地址并没有全部占用，没有占用的地址也不可使用，读

这些地址将得到一个随意的数值。而写这些地址单元不能得到预期的结果。

不要用软件访问这些未定义的单元，这些单元是留作以后产品扩展用途的，

复位后这些新的位将为0。

中断寄存器：各个中断控制位于IE寄存器，5个中断源的中断优先级控制位

于IP寄存器。

表3-2 AUXR辅助寄存器

双数据指针寄存器：为了便于访问内部和外部数据存储器，提供两个16位数据指针寄存器： DP0位于SFR（特殊功能寄存器）区块中的地址82H - 83H和DP1位于84H - 85H 。当SFR中的位DPS = 0选择DP0，而DPS=1则选择DP1 。用户应在访问相应的数据指针寄存器前初始化DPS位。

电源空闲标志：电源空闲标志（POF）在特殊功能寄存器SFR中PCON的第四位（PCON.4）,电源打开时POF置“1”，它可由软件设置睡眠转台并不为复位所影响。

4 存储器结构

MCS-51单片机内核采用程序存储器和数据存储器空间分开的结构，均具有64KB外部程序和数据的寻址空间。

4.1 程序存储器

如果的EA引脚接地（GND），全部程序都可以执行外部存储器。在AT89S51 ，如果EA连接到电源+（VCC），程序首先执行地址从0000H到FFFH内部存储器，在执行地址从1000H到FFFFH的外部程序存储器。

4.2 数据存储器

AT89S51具有128字节的内部RAM 。这128字节都可以通过直接和间接寻

址方式访问，堆栈操作可利用间接寻址方式进行，因此， 128字节都可以可作

为堆栈空间。

5 看门狗定时器（WDT）

看门狗定时器（WDT）是为了解决CPU程序运行时可能进入混乱或死循环而

设置，它由一个14bit计数器和看门狗定时器复位SFR（WDTRST）构成。外部复位时，看门狗定时器（WDT）默认为关闭状态，要打开WDT，用户必须按顺序将

01EH和0E1H写到WDTRST寄存器（SFR地址为0A6H），当启动了WDT，它会随警惕振荡器在每个机器周期计数，除了硬件复位或WDT溢出复位外没有其它方法关闭WDT，当WDT溢出，将使RST引脚输出高电平的复位脉冲。

5.1使用看门狗定时器（WDT）

用户在打开WDT时，需要按次序将01EH和0E1H写到WDTRST寄存器(SFR的地址为0A6H)，当WDT打开后，需要在一定的时候将01EH和0E1H写道WDTRST

寄存器以避免WDT计数溢出。14位WDT计数器达到16383（3FFFH），WDT将溢

出并使用器件复位。WDT打开时，它会随着晶体振荡器在每个机器周期计数，这意味着用户必须在小于每个16383机器周期内复位WDT，也即写01EH和0E1H到WDTRST寄存器，WDTRST为只写寄存器。WDT计数器既不可读也不可写，当WDT

溢出时，通常将使RST引脚输出高电平的复位脉冲。复位脉冲持续时间为98xTosc，而Tosc=1/Fosc(晶体振荡频率)。为使WDT工作最优化，必须在合适的程序代码时间段周期地复位WDT防止WDT溢出。

5.2掉电和空闲模式下的WDT

掉电时期，晶体振荡停止，看门狗定时器也停止。掉电模式下，用户不嗯那个在复位看门狗定时器。有两种方法可以推出掉电模式：硬件复位或通过激活外部中断，当硬件复位退出掉电模式时，处理看门狗定时器可像通常的上电复位一

样。当由中断退出掉电模式时则有所不同，中断低电平状态持续到晶体振荡稳定，当中断电平变为高电平事即可相应中断服务。以防止中断误复位，当器件复位，中断引脚持续为低时，看门狗定时器并未开始计数，知道中断引脚被拉高时为止。这为在掉电模式下的中断执行中断服务程序而设置。为保证看门狗定时器在退出掉电模式时极端情况下不溢出，最好在进入掉电模式前复位看门狗定时器。在进入空闲模式前，看门狗定时器打开时，WDT是否继续计数由SFR中的AUXR的WDIDLE位决定，在IDLE期间（位WDIDLE=0）默认状态是继续计数。为防止AT89S51从空闲模式中复位，用户应该周期性地设置定时器，重新进入空闲模式。

当WDIDLE位被置位，在空闲模式中看门狗定时器将停止计数，直到从空闲(IDLE)模式中退出重新开始计数。

6 中断

AT89S51共有五个中断向量：两个外部中断（ INT0和INT1 ），两个定时器中断（Timer0和Timer1)和一个串行中断。这些中断都如图6-1 。这些中断源各自的禁止和使能位参见特殊功能寄存器的IE。IE也包含总中断控制位EA，EA清0，将关闭所有中断。

值得注意的是表6-1中的IE.6和IE.5没有定义，用户不要访问这些位，它是保留为以后的AT89产品扩展用途。定时器0和定时器1的中断标志TF0和TF1，它是定时器溢出时的S5P2时序周期被置位，该标志保留至下个时序周期。

图6-1 中断源方框图

7 振荡器特性

AT89S51中有一个用于构成内部振荡器的高增益反相放大器，引脚XTAL1和XTAL2分别是该放大器的输入端和输出端。如图7-1所示。外接石英晶体或陶瓷谐振器都可以使用于反馈元件。用户也可以采用外部时钟，在这种情况下，外部时钟接到XTAL1端，即内部时钟发生器的输入端，XTAL2则悬空，如图7-2所示。由于外部时钟信号是通过一个2分频触发器后作为内部时钟信号的，所以对外部时钟信号的占空比没有特殊要求，但是最小高电平持续时间和最大的低电平时序时间应符合产品技术条件的要求。

图7-1 内部振荡电路 注意：石英晶体时，pF pF C C 10302,1±= 陶瓷滤波器，pF pF C C 10402,!±=

图7-2 外部时钟驱动电路

8 空闲模式

在空闲工作模式状态， CPU保持睡眠状态而所有片内的外设仍然保持激活状态，这种方式由软件产生。此时，片内RAM和所有特殊功能寄存器的内特那个保持不变，空闲模式可由任何语序中断的请求或硬件复位终止。

需要注意的是，当由硬件复位来终止空闲工作模式时，CPU通常是从激活空闲模式那条指令的下一条指令开始继续执行程序的，要完成内部复位操作，硬件复位脉冲要保持两个机器周期有效，在这种情况下，内部禁止CPU访问片内RAM,而允许访问其他端口。为了避免在复位结束时可能对端口产生意外写入，激活空闲模式的那条指令的后一条指令不应该是一条对端口或外部存储器的写入指令。

9 掉电模式

在掉线模式下，振荡器停止工作，进入掉电模式的指令是最后一条被执行的指令，片内RAM和特殊功能寄存器的内容在终止掉电模式前被冻结。退出掉电模式的方法是硬件复位或由处于使能状态的外中断INT0和INT1激活。复位后将重新定义全部特殊功能寄存器，但不改变原来RAM中的内容，在VCC恢复到正常工作电平前，复位应无效，且必须保持一定时间以使振荡器重启动并稳定工作。