东南大学信息学院 poc实验报告

Computer Organization and Architecture

COURSE DESIGN

A Parallel Output Controller

------ (POC)

Southeast university

School of Information Science and Engineering

1.Design purpose

a.The purpose of this project is to design and simulate a parallel output controller (POC)

which acts an interface between system bus and printer. The ISE 14.7 EDA tool is

recommended and provided for simulation.

b.Learn about the using of Bi-directional Data Bus (BDB), and use a parallel Bi-directional Data Bus to finish the data transmission between CPU and POC.

2.Introduction and Tasks

POC is one of the most common I/O modules, namely the parallel output controller. It plays the role of an interface between the computer system bus and the peripheral

Figure 1. System structure diagram

As Fig.1 shows the inner connecting of a printer to the system bus through the POC. The - munication between POC and the printer is controlled by a “handshake” protocol given

in Fig.2.

Figure 2. The handshake-timing diagram between POC and the printer The handshaking process is described as follows: When the printer is ready to receive a

char- acter, it holds RDY=1. The POC must then hold a character at PD (parallel data) port and produce a pulse at the terminal TR (transfer request). The printer will change RDY to 0, take the character

at PD and hold RDY at 0 until the character has been printed (e.g. delay 5 or 10ms), then set RDY to 1 again when it is ready to receive the next character.

The buffer register BR is used to temporarily hold a character sent from the processor, which char- acter will be transferred to the printer later.

The status register SR is used for two control

functions:

①SR7 serves as a ready flag to indicate POC is ready or not to receive a new character from the processor.

②SR0 is used to enable the interrupt requests sent by

POC.

In interrupt mode, If SR0=1, then POC will send an interrupt request signal to processor when it is ready to receive a character (i.e., when SR7=1).

If SR0=0, then POC will not

interrupt.

The transfer of a character to POC via the system bus proceeds as follows:

In interrupt mode, SR0 is always

1.

After sending character to printer, POC sets the SR7 to 1, since SR0=1, the interrupt request signal (IRQ) is set to 0, which indicate an effective interrupt signal to the processor.

1、processor sets the value of SR7 &sets the value of

BR

①When the processor detects the effective IRQ signal, the processor directly selects BR and writes a character into BR, (processor will never read the state of SR7, which is different with polling mode.)

②Then the processor sets the SR7 to 0, which indicates that the new character has been written into

BR and not printed

yet.

2、POC reads and sets the value of SR7& handshakes operations with the

printer

①When POC detects that SR7 is set to 0, POC then proceeds to start the handshaking operations with the printer.

②After sending character to printer, POC sets the SR7 to 1, which indicates POC is ready to receive another character from the processor. The transfer cycle can now repeat.（①and ②are same with the polling state）

PS: During the handshaking operations between POC and printer, the processor does not try to access POC until it receives the interrupt request signal

3.The overall connection of the simulated printer and POC expressed in the top module form

Figure 3. The top module form of the project

4.Design description of the simulation input

waveforms

The input and output of CPU,POC and printer are shown below:

Processorj

Pins Descriptio

n

Input

clk Input the clock for the CPU running.

mode Choose the mode for printing.

When mode=’1’,select a interrupt

mode.

IRQ

Receive the interrupt signal IRQ.

When IRQ='1' , new data can be sent.

DIN[7..0] Read data from poc.

DOUT[7..0] Write data into poc.

Output

rw Show the direction of the DOUT[7..0] and DIN[7..0]

When rw='0', read data from POC.

When 'rw'='1', write data to POC.

A0 Control the address read and write on POC.

5.Simulation results

Connection between cpu and poc

Connection between poc and printer

Here are the explanations of the simulation wave:

interrupt mode:

1、In the interrupt mode,mode is always set 1, the print process occures by the IRQ signal from poc.

2、When S(7)=0, IRA send ‘0’ to cpu, it means there is a print requirement and cpu begin to handle it.

3、In the interrupt process RW and A0 are singals from cpu to poc to control the action of poc.

RW=’1’and A0=’1’write data from cpu(D) to poc(BR), means the begin of the interrupt process.

RW=’x’ and A0=’x’ means there is no interrupt requirement .

4、After sending datas to BR and set sr to “00000000”, if RDY=’1’, poc give a impulse in TR to make the printer begin to work. After the TR signal we can see that the input RDY signal from the printer change from 1 to 0, which shows that the TR signal really make the printer work.

5、After data of BR has been transmitted into printer, poc set SR to “10000001” itself to indicate that it comes to ready and can get the next print task.

6、Let data plus 1 to indicate the next new print cycle.

6. Conclusion and Discussions

1、As a parallel output controller ,poc module to act as an interface between cpu and printer. Form the simulation wave, we can see that my program meets the designs requirements.

2、I divide the system into three parts, and one top entity. And I use two way to finish the top entity. One is write program with vhdl language and another is create a schematic type file and connect wire.

3、By designing the POC module, I find it helps to learn how to use of quartus and VHDL for design and simulation.The process of designing also teachs me the importantce of figuring out the struc- ture and timing of the task before programming .

Appendix:

The program of processor:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity processor is

port

(

clk : in std_logic;

IRQ : in std_logic;

DOUT : out std_logic_vector(7 downto 0):="00000000";

RW : out std_logic:='0';--0read,1write

A0 : out std_logic:='0';--0sr,1br

DIN : in std_logic_vector(7 downto 0)

);

end processor;

architecture Behavioral of processor is

signal data:std_logic_vector(7 downto 0):="00000000";

signal mode:std_logic:='1';--默认为中断模式

begin

process(clk)

begin

if clk'event and clk='1' then

if mode='1' then

if IRQ='0' then

A0<='1';

RW<='1';--写入数据到BR

data<=data+"00000001";--代表传输的字符

DOUT<=data;

else

A0<='X';

RW<='X';--读入SR的数据

end if;

end if;

end if;

end process;

end Behavioral;

the program of poc:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use ieee.std_logic_arith.ALL;

use ieee.std_logic_unsigned.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity poc is

port

(

A0 : in std_logic;

RW : in std_logic;

clk : in std_logic;

CS : in std_logic:='1';

RDY : in std_logic;

IRQ : out std_logic:='1';

DOUT : out std_logic_vector(7 downto 0);

PD : out std_logic_vector(7 downto 0);

TR : out std_logic:='0';

DIN : in std_logic_vector(7 downto 0)

);

end poc;

architecture Behavioral of poc is

signal SR : std_logic_vector(7 downto 0):="10000001"; signal BR : std_logic_vector(7 downto 0):="00000000"; signal count:integer range 0 to 5:=0;

type state_type is (s0,s1,s2);

signal state: state_type:=s0;

begin

process(clk)

begin

if clk'event and clk='1' then

TR<='0';

IRQ<='1';

case state is

when s0=>----中断请求信号

if SR(7)='1' then

IRQ<='0';--中断请求

state<=s1;

else

IRQ<='1';

state<=s2;--无中断请求

end if;

when s1=>----读入读出选择

if RW='1' and A0='1' then--cpu写入数据到BR

BR<=DIN;

SR(7)<='0';

state<=s2;

elsif RW='0' and A0='0' then--cpu读入SR的数据

DOUT<=SR;

elsif RW='1' and A0='0' then--cpu写入数据到SR

SR<=DIN;

elsif RW='0' and A0='1' then--cpu读入BR的数据

DOUT<=BR;

end if;

when s2=>----打印机

if RDY='1' then

TR<='1';

PD<=BR;

SR(7)<='1';

end if;

state<=s0;

end case;

end if;

end process;

end Behavioral;

the program of printer:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use ieee.std_logic_arith.ALL;

use ieee.std_logic_unsigned.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity print is

port

(

RDY : out std_logic:='1';

TR : in std_logic;

PD : in std_logic_vector(7 downto 0);

clk : in std_logic

);

end print;

architecture Behavioral of print is

signal count: integer range 0 to 5:=0;

signal data: std_logic_vector(7 downto 0);

signal ready:std_logic;

begin

process(clk,TR)

begin

if clk'event and clk='1' then

if TR='1' then

RDY<='0';

ready<='0';

data<=PD;

else

if ready='0' then

count<=count+1;

if count=5 then

RDY<='1';

ready<='1';

count<=0;

end if;

end if;

end if;

end if;

end process;

end Behavioral;

connection program:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity top is

port

(

CLK : in std_logic

);

end top;

architecture Behavioral of top is

signal a0:std_logic;

signal irq:std_logic;

signal d1:std_logic_vector(7 downto 0);

signal d2:std_logic_vector(7 downto 0);

signal rw:std_logic;

signal rdy:std_logic;

signal pd:std_logic_vector(7 downto 0);

signal tr:std_logic;

component processor

port

(

clk : in std_logic;

IRQ : in std_logic;

DOUT : out std_logic_vector(7 downto 0):="00000000"; RW : out std_logic:='0';--0read,1write

A0 : out std_logic:='0';--0sr,1br

DIN : in std_logic_vector(7 downto 0)

);

end component;

component poc

port

(

A0 : in std_logic;

RW : in std_logic;

clk : in std_logic;

CS : in std_logic:='1';

RDY : in std_logic;

IRQ : out std_logic:='1';

DOUT : out std_logic_vector(7 downto 0);

PD : out std_logic_vector(7 downto 0);

TR : out std_logic:='0';

DIN : in std_logic_vector(7 downto 0)

);

end component;

component print

port

(

RDY : out std_logic:='1';

TR : in std_logic;

PD : in std_logic_vector(7 downto 0);

clk : in std_logic

);

end component;

begin

u1: processor port map(clk=>CLK,A0=>a0,RW=>rw,IRQ=>irq,DOUT=>d1,DIN=>d2); u2: poc port

map(clk=>CLK,A0=>a0,RW=>rw,IRQ=>irq,DOUT=>d2,DIN=>d1,RDY=>rdy,TR=>tr,PD =>pd);

u3: print port map(clk=>CLK,RDY=>rdy,TR=>tr,PD=>pd);

end Behavioral;